Sony CDX-727 Service Manual ▷ View online
– 45 –
IC202
AT24C16N-10SI-TR
DEVICE
ADDRESS
COMPARATOR
Y DEC
H.V. PUMP/TIMING
DATA RECOVERY
E
2
PROM
SERIAL MUX
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
DATA WORD
ADDR/COUNTER
D
OUT
/ACK
LOGIC
1
2
2
3
4
5
6
7
8
X DEC
VCC
TST
SDL
SDA
A0
A1
A2
A2
GND
COMP
LOAD
LOAD INC
R/W
EN
D
OUT
D
IN
IC301
BA6287F
IC302
BA8272F-E2
IC401
CXD2522Q
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER
DRIVER
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
VWA
ADDRESS MONITOR
WRITE
BASE
COUNTER
READ
BASE
COUNTER
CPU I/F
SELECTOR
TIMING
GEN.
DSP
I/F
DATA
LINKING
CONTROL
DAC
I/F
DIGITAL
OUT
1 2 3 4
5 6 7 8
9 10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
56
55
54
53
52
51 50 49 48 47
57
58
59
60
61
62
63
64
XWIH
AM4
AM3
AM3
AM2
AM1
AM0
VDD
XQOK
GSCR
SCOR
NC
NC
NC
GRST
XRST
WFCK
DIN
C4M
XROI
RFCK
GTOP
BCKI
VSS
DATI
LRCI
WDCI
TEST
XTAO
XTAI
BCK
DATA
LRCK
DOUT
C176
A3
A2
A1
A0
VDD
A9
XRAS
XWE
D1
D0
D3
D2
XCAS
XOE
A8
A7
A6
A5
A4
OSCE
VSS
SPSL
XEMP
SDTO
XSOE
SCK
SDTI
XLT
XRDE
XWRE
DRAM
I/F
– 46 –
IC402
MSM514400D-60TS-K
WRITE
CLOCK
CLOCK
GENERATOR
DATA INPUT
BUFFER
DATA OUTPUT
BUFFER
COLUMN
DECODER
SENSE AMP
I/O GATE
4M BIT
MEMORY
CELL
ROW
DECODER
ADDRESS
BUFFER
PRE-
DECODER
REFRESH
ADDRESS
COUNTER
COUNTER
BOARD
BIAS
GENERATOR
MODE
CONTROL
CLOCK
GENERATOR
1
CLOCK
GENERATOR
2
18
24
25
26
17
16
15
14
5
4
1
2
3
9
10
11
12
13
23
22
DQ1
DQ2
WE
RAS
A9
A0
A1
A0
A1
A2
A3
VCC
VSS
DQ4
DQ3
DQ3
CAS
OE
A8
A7
A6
A5
A4
A4
IC502
KM62256DLG-7LT
IC601
TC9464FN-EL
MEMORY
MATRIX
512X512
ROW
DECODER
BUFFER
1
A14
2
3
4
5
A5
A12
A7
A6
26 A13
25 A8
24
25 A8
24
23 A11
A9
I/O GATE
COLUMN
COLUMN
DECODER
BUFFER
6
A4
7
8
9
10
A0
A3
A2
A1
27
28 VCC
WE
22 OE
21 A10
BUFFER
18 I/O7
17 I/O6
16
17 I/O6
16
I/O4
I/O5
19 I/O8
15
I/O BUFFER
11
12
13
I/O3
I/O1
I/O2
20 CE
14
GND
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
DIGITAL FILTER CIRCUIT
ATTENUATOR OPERATIONAL CIRCUIT
DEEMPHASIS FILTER CIRCUIT
D-
∆
MODULATION CIRCUIT
INTERFACE
CIRCUIT
TEST
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
ANALOG
FILTER
TIMING
GENERATOR
OSC
MICROCOMPUTER
INTERFACE
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
ANALOG
FILTER
1
2
3 4
5
6
7
8
9
10
20
19
18
17
16
15
14 13
12
11
21
22
23
24
LRCK
BCK
DATA
HS
(SM)
ATT
(EMP)
SH
(BS)
LA
VDX
XO
XI
GNDX
MCK
VDD
T1
P/S
VDA
RO
GNDA
VR
GNDA
LO
GNDD
ZD
VDA
– 47 –
7-13.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC201 CXP84332-210Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Function
1 to 3
—
O
Not used (open)
4
CH.F
O
Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)
“L” active *1
“L” active *1
5
CH.R
O
Motor drive signal (save direction) output to the chucking motor drive (IC52)
“L” active *1
“L” active *1
6
LOAD2
I
Chucking end detect switch (SW11) input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
7
LOAD1
I
Save end detect switch (SW12) input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
8
SENS2
I
Internal status signal (sense signal) input from the CXA1992BR (IC11)
9
LIM.SW
I
Sled limit in detect switch (SW1) input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
10
EE.INIT
I
Initialize signal input for the EEPROM (IC202) “H”: format Fixed at “L” in this set
11
EE.CLK
O
Serial data transfer clock signal output to the EEPROM (IC202)
12
EE.DATA
I/O
Two-way data bus with the EEPROM (IC202)
13 to 19
—
O
Not used (open)
20
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
21
XRST
O
System reset signal output to the CXA1992BR (IC11), CXD2530Q (IC101) and CXD2522Q
(IC401) “L”: reset
(IC401) “L”: reset
22
FOK
I
Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK
23
SENS
I
Internal status signal (sense signal) input from the CXD2530Q (IC101)
24
GFS
I
Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK
25
GRSRT
O
Reset signal output to the CXD2522Q (IC401) “L”: reset
26
XQOK
O
Subcode Q OK pulse signal output to the CXD2522Q (IC401) “L” active
27
SDTI
I
ESP status signal input from the CXD2522Q (IC401)
28
XSOE
O
ESP status read enable signal output to the CXD2522Q (IC401) “L” active
29
ESPXLT
O
ESP latch pulse signal output to the CXD2522Q (IC401) “L” active
30
RST
I
System reset signal input from the SONY bus interface (IC302) and reset signal generator
(IC304) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
(IC304) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL
I
Main system clock input terminal (8 MHz)
32
XTAL
O
Main system clock output terminal (8 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal Not used (open)
35
TEX
I
Sub system clock input terminal Not used (fixed at “L”)
36
AVSS
—
Ground terminal (for A/D converter)
37
AVREF
I
Reference voltage (+5V) input terminal (for A/D converter)
38
MCK
I
Input of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator
position (A/D input)
position (A/D input)
39
EHS
I
Elevator height position detect input from the RV202 (elevator height sensor) (A/D input)
40
MODEL
I
Setting terminal for the destination (fixed at “H” in this set)
41
XRDE
O
D-RAM read enable signal output to the CXD2522Q (IC401) “L” active
42
XWRE
O
D-RAM write enable signal output to the CXD2522Q (IC401) “L” active
43
A.MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
44
EMP
O
Emphasis mode output to the D/A converter (IC601) “H”: emphasis on
45
ML
O
Fast speed dubbing control signal output to the D/A converter (IC601) “L”: fast speed
46
GRSCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2522Q (IC401)
– 48 –
*1 chucking motor (M103) control
STOP
LOAD
CHUCKING
SAVE
BRAKE
CH.F (pin 4)
“H”
“L”
“H”
“L”
CH.R (pin 5)
“H”
“H”
“L”
“L”
Mode
Terminal
*2 elevator motor (M104) control
STOP
ELEVATOR
UP
ELEVATOR
DOWN
BRAKE
ELV.F (pin %•)
“H”
“L”
“H”
“L”
ELV.R (pin &º)
“H”
“H”
“L”
“L”
Mode
Terminal
Pin No.
Pin Name
I/O
Function
47
D/A.RESET
O
Reset signal output terminal “L”: reset Not used (open)
48
SCK
I
Serial data transfer clock signal input from the SONY bus interface (IC302)
49
SI
I
Serial data input from the SONY bus interface (IC302)
50
SO
O
Serial data output to the SONY bus interface (IC302)
51
SCLK
O
Subcode Q data reading clock signal output to the CXD2530Q (IC101)
52
SUBQ
I
Subcode Q data input from the CXD2530Q (IC101)
53
—
O
Not used (open)
54
C.OUT
I
Track number count signal input from the CXA1992BR (IC11)
55
BUS.ON
I
Bus on/off control signal input from the SONY bus interface (IC302) “H”: bus on
56
—
I
Not used (open)
57
MGLK
I
Magazine eject operation completion detect switch (SW201) input “L”: eject completed
58
ELV.F
O
Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
“L” active *2
“L” active *2
59
—
O
Not used (open)
60
MAG.SW
I
Magazine in/out detect switch (SW202) input “L”: magazine detected
61
BU.CHK
I
Battery detection signal input terminal “H”: battery on
62
W.UP
I
Bus on or eject switch (SW301) input terminal “H”: bus on or eject switch pushing
63
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
64
EJECT
I
Eject switch (SW301) input terminal “H” active
65
CD.CLK
O
Serial data transfer clock signal output to the CXD2530Q (IC101) and CXD2522Q (IC401)
66
CD.XLT
O
Serial data latch pulse signal output to the CXD2530Q (IC101)
67
CD.DATA
O
Serial data output to the CXD2530Q (IC101) and CXD2522Q (IC401)
68
CD.ON
O
D/A converter and servo section power supply on/off control signal output “H”: power on
69
ELV.ON
O
Mechanism deck section power supply on/off control signal output “H”: power on
70
ELV.R
O
Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active *2
“L” active *2
71
—
O
Not used (open)
72
VDD
—
Power supply terminal (+5V)
73
NC (VDD)
—
Connected to the power supply (+5V)
74
BUSY
I
Busy monitor input from the CD text decoder (IC501) “L”: busy status
75
RESET
O
Reset signal output to the CD text decoder (IC501) “L”: reset
76
REQ
I
Data request signal input from the CD text decoder (IC501) “L” active
77
CCCLK
O
Command clock signal output to the CD text decoder (IC501)
78
CSO
O
Command data output to the CD text decoder (IC501)
79
CSI
I
Command data input from the CD text decoder (IC501)
80
—
I
Not used (open)
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