Sony ZS-XN30 Service Manual ▷ View online
33
ZS-XN30
– TUNER Board –
IC1
TA2149BN
RF GND
3
2
1
IF REQ
AM
MIX
FM RFIN
AM LOW CUT
5
4
MIX OUT
VCC
AM IF IN
8
7
6
FM IF IN
GND
10
9
AGC
QUAD
12
11
R-OUT
L-OUT
FM RFOUT
22
23
24
20
21
17
18
19
15
16
13
14
AM RFIN
RF VCC
FM OSC
ST LED
OSC OUT
AM OSC
IF REQ
LPF1
MPX IN
DET OUT
LPF2
FM
MIX
FM
OSC
LEVEL
DET
AM
DET
MUTE
FM
DET
ST/MO
FM/AM
AM
OSC
AGC
SW
ST
1/8
BUFF
BUFF
DIVIDE
DECODE
VCO
IF BUFF
AF BUFF
AF
FM RF
AM IF
FM IF
1/1 OR
1/16
IC2
LC72137M-TLM-E
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
19
20
UNLOCK
DETECTOR
POWER ON
RESET
UNIVERSAL
COUNTER
CCB
I/F
CE
DI
CL
DO
XOUT
AOUT
XIN
AIN
PD
VSS
VDD
B04
FMIN
AMIN
B01
B02
B03
I01
I02
IFIN
PHASE
DETECTOR
CHARGE
PUMP
REFERENCE
DIVIDER
SWALLOW
COUNTER
1/16,1/17
4BITS
12BITS
PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
1/2
17
18
34
ZS-XN30
– CONTROL Board –
IC804
BR24C01AF-W
1
2
3
4
5
6
7
8
LOGIC
DOUT/ACK
X DEC
DATA REGISTER
SERIAL MUX
EEPROM
ADDRESS/COUNTER
DATA WORD
LOGIC
CONTROL
SERIAL
LOGIC
STOP
START
H.V.PUMP/TIMING
Y DEC
DOUT
R/W
DIN
INC
LOAD
EN
VCC
TEST
SCL
SDA
NC
NC
NC
GND
– AUDIO Board –
IC301
PT2257-S
1
2
4
8
7
6
5
LIN
SCL
LOUT
VDD
RIN
ROUT
SDA
+
−
−
+
−
−
+
−
3
VSS
CONTROL UNIT
IC302
BA5417
STANDBY
T.S.D.
BS
FILTER
PRE GND2
PRE GND1
NF2
IN2
IN1
NF1
FIL
TER
STBY
POWER GND
BS1
OUT1
VCC
OUT2
10
3 4 5
6
BS
BS2
2
NC
1
8
9
7
11 12
13
14 15
+
–
–
+
–
–
3
2
5
OVERCURRENT
PROTECT
CIRCUIT
REFERENCE
VOLTAGE
ERROR
AMP
SINK
DRIVER
4
1
VOUT
VIN
ON/OFF
VSS
EXT
SOURCE
POWER
SUPPLY
IC303
S-816A33AMC-BAI-T2
35
ZS-XN30
•
IC Pin Function Description
CD BOARD IC702 CXD3029R (CD DSP)
Pin No.
Pin Name
I/O
Description
1
XRAS
O
Row address strobe signal output to the D-RAM
2
XWE
O
Data input enable signal output to the D-RAM
3 to 6
D1, D0, D3, D2
I/O
Two-way data bus with the D-RAM
7, 8
TEST1, TEST2
O
Not used
9
XCAS
O
Column address strobe signal output to the D-RAM
10
WFCK
O
Not used
11 to 13
A9 to A7
O
Address signal output to the D-RAM
14
DVSS
—
Ground terminal
15 to 17
A6 to A4
O
Address signal output to the D-RAM
18
XRDE
I
Read enable signal input from the MP3 decoder
19
VDD0
—
Power supply terminal (+3.3V)
20
CLOK
I
Serial data transfer clock signal input from the system controller
21
DATA
I
Serial data input from the system controller
22
SENS
O
SENS signal output to the system controller
23
XLAT
I
Serial data latch pulse signal input from the system controller
24
XSOE
I
Serial data output enable signal input from the system controller
25
SYSM
I
Analog muting on/off control signal input from the system controller “H”: muting on
fixed at “L” in this set
fixed at “L” in this set
26
WDCK
O
Not used
27
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller
28
XRST
I
Reset signal input from the system controller “L”: reset
29
PWMI
I
Not used
30
XQOK
I
Not used
31
XWRE
I
Not used
32
R8M
O
System clock output terminal Not used
33
VSS0
—
Ground terminal
34
SQCK
I
SQSO readout clock signal input terminal Not used
35
SCLK
I
SENS serial data read clock signal input terminal Not used
36
SQSO
O
Not used
37
XEMP
O
Not used
38
XWIH
O
Not used
39
SBSO
O
Not used
40
EXCK
O
SQSO readout clock signal output terminal Not used
41
XTSL
I
Input terminal for the system clock frequency setting fixed at “L” in this set
42
HVSS
—
Ground terminal
43
HPL
O
Not used
44
HPR
O
Not used
45
HPVDD
—
Power supply terminal (+3.3V)
46
XVDD
—
Power supply terminal (+3.3V)
47
XTAI
I
System clock input terminal (16.9344 MHz)
48
XTAO
O
System clock output terminal (16.9344 MHz)
49
XVSS
—
Ground terminal
50
AVDD1
—
Power supply terminal (+3.3V)
51
AOUT1
O
L-ch analog audio signal output terminal
52
VREFL
O
L-ch reference voltage output terminal
36
ZS-XN30
Pin No.
Pin Name
I/O
Description
53, 54
AVSS1, AVSS2
—
Ground terminal
55
VREFR
O
R-ch reference voltage output terminal
56
AOUT2
O
R-ch analog audio signal output terminal
57
AVDD2
—
Power supply terminal (+3.3V)
58
TES1
I
Input terminal for the test (fixed at “L”)
59
TEST
I
Input terminal for the test (fixed at “L”)
60
VSS1
—
Ground terminal
61
LRMU
O
Muting on/off control signal output terminal Not used
62
DOUT
O
Not used
63
ATSK
I/O
Not used
64
DFCT
I/O
Not used
65
FOK
O
Focus OK signal output to the system controller
66
MIRR
I/O
Not used
67
COUT
I/O
Not used
68
C2PO/MNT3/
GTOP
O
Not used
69
GFS/MNT2/
XROF
O
GFS signal output to the system controller
70
XUGF/MNT0/
RFCK
O
Not used
71
XPCK/MNT1/
XPCK
O
Not used
72
VDD1
—
Power supply terminal (+3.3V)
73
PCO
O
Charge pump output terminal for master PLL
74
FILI
I
Filter input terminal for master PLL
75
FILO
O
Filter output terminal for master PLL
76
CLTV
I
VCO1 control voltage input terminal for multiplier
77
VCTL
I
VCO2 control voltage input terminal for broad-band EFM PLL
78
VPCO
O
Charge pump output terminal for broad-band EFM PLL
79
AVSS3
—
Ground terminal
80
ASYO
O
EFM full-swing output terminal
81
ASYI
I
Asymmetry comparator voltage input terminal
82
BIAS
I
Asymmetry circuit constant current input terminal
83
AVDD3
—
Power supply terminal (+3.3V)
84
RFAC
I
EFM signal input from the RF amplifier
85
AVDD0
—
Power supply terminal (+3.3V)
86
IGEN
I
Stabilized current input terminal
87
AVSS0
—
Ground terminal
88
RFDC
I
RF signal input from the RF amplifier
89
CE
I
Chip enable signal input terminal Not used
90
TE
I
Tracking error signal input from the RF amplifier
91
SE
I
Sled error signal input from the RF amplifier
92
FE
I
Focus error signal input from the RF amplifier
93
VC
I
Middle point voltage input terminal
94
VSS2
—
Ground terminal
95
FRDR
O
Focus servo drive signal (–) output to the coil/motor drive
96
FFDR
O
Focus setvo drive signal (+) output to the coil/motor drive
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