Sony ZS-R100CP Service Manual ▷ View online
ZS-R100CP
41
• IC Pin Function Description
CD BOARD IC501 LC87F1JJ4AU-SQFP-H (USB/SD CARD CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
PT3/INT3
O
Not used
2
RES
I
Reset signal input from the system controller “L”: reset
3
XT1
I
Sub system clock input terminal Not used
4
XT2
O
Sub system clock output terminal Not used
5
VSS1
-
Ground terminal
6
CF1
I
Main system clock input terminal (12 MHz)
7
CF2
O
Main system clock output terminal (12 MHz)
8
VDD1
-
Power supply terminal (+3.3V)
9
SO
O
Serial data output to the CD DSP
10
SI
I
Serial data input from the CD DSP
11
SCK
O
Serial data transfer clock signal output to the CD DSP
12
P13/SO1
O
Not used
13
P14/SI1
O
Not used
14
P15/SCK1
O
Not used
15
CE
O
Chip enable signal output to the CD DSP
16
P17/T1PWMH
O
Not used
17
PWM1/MCLKI
O
Not used
18
PWM0/MCLKO
O
Not used
19
VDD2
-
Power supply terminal (+3.3V)
20
VSS2
-
Ground terminal
21
PO0/AN0
O
Not used
22
PO1/AN1
O
Not used
23 to 25
DBGP0 to DBGP2
I/O
Writing terminal
26
SDAT
I
Audio data input from the CD DSP
27
BCLK
I
Bit clock signal input from the CD DSP
28
LRCK
I
L/R sampling clock signal input from the CD DSP
29
CARD DET
I
SD card detection signal input terminal
30
CD/DATA3
I/O
Two-way data bus with the SD card
31
STDATA0
O
Stream data output to the CD DSP
32
PCMREQ
O
Audio data request signal output to the CD DSP
33
STCKO
O
Stream data transfer clock signal output to the CD DSP
34
SD DATA0
I/O
Two-way data bus with the SD card
35
SD CMD
I/O
Command signal output to the SD card and response signal input from the SD card
36
SD CLK
O
Serial data transfer clock signal output to the SD card
37
UHD−
I/O
Two-way USB data (−) bus with the USB connector
38
UHD+
I/O
Two-way USB data (+) bus with the USB connector
39
VDD3
-
Power supply terminal (+3.3V)
40
VSS3
-
Ground terminal
41
UFILT
-
PLL fi lter circuit connection terminal for USB interface
42
AFILT
-
PLL fi lter circuit connection terminal for audio interface
43
P32
O
Not used
44
URX1
I
Serial data input from the system controller
45
UTX1
O
Serial data output to the system controller
46
STREQ0
I
Stream data request signal input from the CD DSP
47
USB-SLEEP
I
Sleep signal input from the system controller
48
SD WRITE PROTECT
I
SD card writing protect detection signal input terminal
ZS-R100CP
42
CD BOARD IC702 LC786953W-US-H (CD DSP)
Pin No.
Pin Name
I/O
Description
1 to 6
AT0 to AT5
I
Analog test terminal
7
EFMIN
I
RF signal input terminal
8
RFOUT
O
RF signal output terminal
9
LPF
-
LPF capacitor connection terminal for DC level detection of RF signal
10
PHLPF
-
LPF capacitor connection terminal for defect detection
11
AIN
I
Main beam (A) input from the optical pick-up block
12
CIN
I
Main beam (C) input from the optical pick-up block
13
BIN
I
Main beam (B) input from the optical pick-up block
14
DIN
I
Main beam (D) input from the optical pick-up block
15
SLCISET
-
Resistor connection terminal for current setting of slice level control signal output
16
AT6
I
Analog test terminal
17
RFMON
-
LSI internal analog signal monitor terminal
18
VREF
O
Reference voltage output terminal
19
JITTC
-
Capacitor connection terminal for jitter detction
20
AT7
I
Analog test terminal
21
EIN
I
Sub beam (E) input from the optical pick-up block
22
FIN
I
Sub beam (F) input from the optical pick-up block
23
PCNCNT
I
Control voltage input terminal for EFM PLL charge pump
24
TEOUT
O
Tracking error signal output terminal
25
TEIN
I
Tracking error signal input terminal
26
LDO
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
“H”: laser diode on
27
LDS
I
Light amount monitor input from the laser diode of optical pick-up block
28
AVSS
-
Ground terminal (for analog)
29 to 36
AT8 to AT15
I
Analog test terminal
37
AVDD
-
Power supply terminal (+3.3V) (for analog)
38
FDO
O
Focus coil drive signal output terminal
39
TDO
O
Tracking coil drive signal output terminal
40
SLDO
O
Sled motor drive signal output terminal
41
SPDO
O
Spindle motor drive signal output terminal
42
VVSS1
-
Ground terminal (for internal VCO)
43, 44
PDOUT1, PDOUT0
O
Phase comparison output terminal for internal VCO control
45
PCKIST
-
Resistor connection terminal for current setting of PDOUT1 and PDOUT0 output
46
VVDD1
-
Power supply terminal (+3.3V) (for internal VCO)
47
SDDQML
O
Data mask signal output to the SD-RAM (lower byte)
48
SDMEB
O
Write enable signal output to the SD-RAM
49
SDCASB
O
Column address strobe signal output to the SD-RAM
50
SDRASB
O
Low address strobe signal output to the SD-RAM
51
SDCSB
O
Chip select signal output to the SD-RAM
52 to 57
SDADRS11,
SDADRS10, SDADRS0
to SDADRS3
O
Address signal output to the SD-RAM
58
NC
-
Not used
59
DVDD
-
Power supply terminal (+3.3V) (for digital)
60
DVSS
-
Ground terminal (for digital)
61
DVDD15
-
Capacitor connection terminal for internal regulator
62 to 67
SDADRS4 to
SDADRS9
O
Address signal output to the SD-RAM
68
SDCKE
O
Clock enable signal output to the SD-RAM
69
SDCLK
O
System clock signal output to the SD-RAM
70
SDDQMU
O
Data mask signal output to the SD-RAM (upper byte)
71
VVDD3
-
Power supply terminal (+3.3V) (for internal PLL)
72
VVSS3
-
Ground terminal (for internal PLL)
73, 74
NC
-
Not used
75, 76
SDBA0, SDBA1
O
Bank address signal output to the SD-RAM
77
CONT5
O
Not used
78
CONT3
I
Limit in detectino switch input from the optical pick-up block
79
DEFECT
O
Defect detection signal output terminal Not used
80
DVDD
-
Power supply terminal (+3.3V) (for digital)
ZS-R100CP
43
Pin No.
Pin Name
I/O
Description
81
DVSS
-
Ground terminal (for digital)
82
FSEQ
O
CD sync signal detection output terminal Not used
83
C2F
O
C2 error signal output terminal Not used
84
CE
I
Chip enable signal input from the USB/SD card controller and system controller
85
CL
I
Serial data transfer clock signal input from the USB/SD card controller and system controller
86
DI
I
Serial data input from the USB/SD card controller and system controller
87
DO
O
Serial data output to the USB/SD card controller and system controller
88
RESB
I
Reset signal input from the system controller “L”: reset
89
INTB0/SUB_READY0
O
Interrupt signal or sub ready signal output terminal Not used
90
INTB1
O
Interrupt signal output terminal Not used
91
CPMODE
I
Error detection mode setting terminal “H”: detection mode on Fixed at “L” in this unit
92
CONT2/CES
O
Command enable signal output terminal Not used
93
CONT1/CPERR
O
Communication error detection output terminal Not used
94
CONT0
O
Not used
95
MODE
I
Operation mode setting terminal “H”: internal sequencer on Fixed at “L” in this unit
96
STREQ0
O
Stream data request signal output to the USB/SD card
97
STCK0
I
Stream data transfer clock signal input from the USB/SD card
98
SDATA0
I
Stream data input from the USB/SD card
99
STREQ1
O
L/R sampling clock signal output to the A/D converter
100
STCK1
O
Bit clock signal output to the A/D converter
101
SDATA1
I
Audio data input from the A/D converter
102
TEST
I
Input terminal for the test
103
DATA
O
Audio data output terminal Not used
104
DATACK
O
Audio bit clock signal output terminal Not used
105
LRCY
O
Audio L/R sampling clock signal output terminal Not used
106
DVSS
-
Ground terminal (for digital)
107, 108
CONT7, CONT6
O
Not used
109
DVDD
-
Power supply terminal (+3.3V) (for digital)
110
PCMLRCY
O
L/R sampling clock signal output to the USB/SD card
111
PCMBCK
O
Bit clock signal output to the USB/SD card
112
PCMDATA
O
Audio data output to the USB/SD card
113
PCMREQ
I
Audio data request signal input from the USB/SD card
114 to 121
SDATA8 to SDATA15
I/O
Two-way data bus with the SD-RAM
122
DVDD15
-
Capacitor connection terminal for internal regulator
123
DVSS
-
Ground terminal (for digital)
124
DVDD
-
Power supply terminal (+3.3V) (for digital)
125 to 132
SDATA0 to SDATA7
I/O
Two-way data bus with the SD-RAM
133
DOUT
O
Master clock signal output to the A/D converter
134
CONT4
O
Not used
135
XVSS
-
Ground terminal (for oscillation circuit)
136
XOUT
O
System clock output terminal (16.934 MHz)
137
XIN
I
System clock input terminal (16.934 MHz)
138
XVDD
-
Power supply terminal (+3.3V) (for oscillation circuit)
139
LRVDD
-
Power supply terminal (+3.3V) (for L/R channel)
140
LCHO
O
Audio data (L-ch) output to the electrical volume
141
LRREF
O
Reference voltage output terminal (for L/R channel)
142
RCHO
O
Audio data (R-ch) output to the electrical volume
143
LRVSS
-
Ground terminal (for L/R channel)
144
SLCO
O
Slice level control signal output terminal
ZS-R100CP
44
MAIN BOARD IC801 LC87F5VP6AU-QIP-H (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 3
I-KEY 1 to I-KEY 3
I
Top panel key input terminal (A/D input)
4
I-AC CHECK
I
AC/DC input detection signal input terminal “L”: AC, “H”: DC
5
I-LCD-INT
I
Interrupt signal input from the liquid crystal display
6
I-WAKE UP
I
Key wake-up signal input terminal
7
I-RMC
I
SIRCS signal input terminal Not used
8
I-RES
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
9
XT1
I
Sub system clock input terminal (32.768 kHz)
10
XT2
O
Sub system clock output terminal (32.768 kHz)
11
VSS1
-
Ground terminal
12
CF1
I
Main system clock input terminal (12 MHz)
13
CF2
O
Main system clock output terminal (12 MHz)
14
VDD1
-
Power supply terminal (+3.3V)
15, 16
O-CLOCK SHIFT 1,
O-CLOCK SHIFT 2
O
Clock shift signal output terminal
17
I-KEY 4
I
Top panel key input terminal (A/D input)
18
I-KEY 5
I
Front panel key input terminal (A/D input)
19
I-BATT-CHK
I
Battery voltage detection signal input terminal for back-up
20
I-VH-CHK
I
Main power supply voltage detection signal input terminal
21
I-REG6V-CHK
I
+6V regulator output power supply voltage detection signal input terminal
22
I-CD3.3V-CHK
I
CD section +3.3V power supply voltage detection signal input terminal
23
O-LCD-RS
O
Resister selection signal output to the liquid crystal display
24
O-LCD-DATA
O
Serial data output to the liquid crystal display
25
O-LCD-SCL
O
Serial data transfer clock signal output to the liquid crystal display
26
O-CD-DO
O
Serial data output to the CD DSP
27
I-CD-DI
I
Serial data input from the CD DSP
28
O-CD-CLK
O
Serial data transfer clock signal output to the CD DSP
29
O-LCD-CS
O
Chip select signal output to the liquid crystal display
30
O-BUZZER
O
Buzzer sound output terminal
31
NC
O
Not used
32
I-CD LID
I
CD lid open/close detection signal input terminal “L”: CD lid is closed, “H”: CD lid is opened
33
I-JOG-B
I
Jog dial pulse input from the rotary encoder (B phase input) (for VOLUME)
34
I-JOG-A
I
Jog dial pulse input from the rotary encoder (A phase input) (for VOLUME)
35
O-LCD-RST
O
Reset signal output to the liquid crystal display “L”: reset
36
O-USB SLEEP
O
Sleep signal output to the USB/SD card controller
37
O-USB RES
O
Reset signal output to the USB/SD card controller “L”: reset
38
O-CD RES
O
Reset signal output to the CD DSP “L”: reset
39
VSS4
-
Ground terminal
40
VDD4
-
Power supply terminal (+3.3V)
41
I-SUFFIX 1
I
Destination setting terminal Fixed at “L” in this unit
42
I-SUFFIX 2
I
Destination setting terminal Fixed at “H” in this unit
43
NC
O
Not used
44
O-CD CE
O
Chip enable signal output to the CD DSP
45
NC
O
Not used
46
O-ADC-PON
O
Power down signal output to the A/D converter “L”: power down
47
M-MUTE
O
Muting on/off control signal output to the coil/motor driver “L”: muting on
48 to 54
NC
O
Not used
55
VDD2
-
Power supply terminal (+3.3V)
56
VSS2
-
Ground terminal
57, 58
NC
O
Not used
59
I-TU-INT
I
Interrupt signal input from the FM/AM receiver
60
I-TONE-DEC
I
Tone decoder detection signal input terminal Not used
61
O-TUNER
O
Tuner section power supply on/off control signal output terminal “H”: power on
62
O-TU RST
O
Reset signal output to the FM/AM receiver “L”: reset
63, 64
NC
O
Not used
65
TUNER-SCL
O
Serial data transfer clock signal output to the FM/AM receiver
66
TUNER-SDA
I/O
Two-way data bus with the FM/AM receiver
67
VOL-SCL
O
Serial data transfer clock signal output to the electrical volume
68
VOL-SDA
I/O
Two-way data bus with the electrical volume
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