Sony ZS-M30 Service Manual ▷ View online
31
ZS-M30
• MD BOARD IC 504 CXD2654R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
1
MNT0 (FOK)
O
Focus OK signal output to the MD mechanism controller (IC601)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller (IC601)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller (IC601)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC601)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC601)
6
SCLK
I (S) Serial data transfer clock signal input from the MD mechanism controller (IC601)
7
XLAT
I (S) Serial data latch pulse signal input from the MD mechanism controller (IC601)
8
SRDT
O (3) Reading serial data signal output to the MD mechanism controller (IC601)
9
SENS
O (3) Internal status (SENSE) output to the MD mechanism controller (IC601)
10
XRST
I (S) Reset signal input from the MD mechanism controller (IC601) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC601)
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism
controller(IC601) “L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the MD mechanism controller (IC601)“L”:
playback mode, “H”: recording mode
14
XINT
O
Interrupt status output to the MD mechanism controller (IC601)
15
TX
I
Recording data output enable signal input from the MD mechanism controller(IC601)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512 Fs = 45.1584 MHz) input terminal
17
OSCO
O
System clock signal (512 Fs = 45.1584 MHz) output terminal
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode (for digital optical input) Not
used
20
DIN1
I
Digital audio signal input terminal when recording mode (for digital optical input)
21
DOUT
O
Digital audio signal output terminal when playback mode (for digital optical output)
Not used
22
DATAI
I
Serial data input terminal Not used (fixed at “L”)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “L”)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “L”)
25
ADDT
I
Recording data input from the A/D, D/A converter (IC604)
26
DADI
I
Playback data input from the A/D, D/A converter (IC604)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC604)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC604)
29
FS256
O
Clock signal (11.2896 MHz) output terminal
30
DVDD
—
Power supply terminal (+3.3 V) (digital system)
31 – 34
A03
O
A00 O Address signal output to the D-RAM (IC505)
35
A10
O
Address signal output to the external D-RAM Not used (open)
36 – 40
A04 – A08
O
Address signal output to the D-RAM (IC505)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC505) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC505) “L” active
45
A09
O
Address signal output to the D-RAM (IC505)
Pin No.
Pin Name
I/O
Pin Description
32
ZS-M30
46
XRAS
O
Row address strobe signal output to the D-RAM (IC505) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC505) “L” active
48
D1
I/O
49
D0
I/O
Two-way data bus with the D-RAM (IC505)
50
D2
I/O
51
D3
I/O
52
MVCI
I (S) Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A) Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3 V) (analog system)
56
BIAS
I (A) Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A) Playback EFM RF signal input from the CXA2523AR (IC502)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3) Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A) Filter input for master clock of the recording/playback master PLL
61
FILO
O (A) Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A) Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A) Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC502)
64
BOTM
I (A) Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC502)
65
ABCD
I (A) Light amount signal (ABCD) input form the CXA2523AR (IC502)
66
FE
I (A) Focus error signal input from the CXA2523AR (IC502)
67
AUX1
I (A) Auxiliary signal (I3 signal/temperature signal) input from the CXA2523AR (IC502)
68
VC
I (A) Middle point voltage (+1.65 V) input from the CXA2523AR (IC502)
69
ADIO
O (A) Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3 V) (analog system)
71
ADRT
I (A) A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A) A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A) Sled error signal input from the CXA2523AR (IC502)
75
TE
I (A) Tracking error signal input from the CXA2523AR (IC502)
76
DCHG
I (A) Connected to the +3.3 V power supply
77
APC
I (A) Error signal input for the laser automatic power control Not used (fixed at “H”)
78
ADFG
I (S) ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC502)
79
F0CNT
O
Filter f0 control signal output to the CXA2523AR (IC502)
80
XLRF
O
Serial data latch pulse signal output to the CXA2523AR (IC502)
81
CKRF
O
Serial data transfer clock signal output to the CXA2523AR (IC502)
82
DTRF
O
Writing serial data output to the CXA2523AR (IC502)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic
powercontrol
84
TESTO
—
Not used (OPEN)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC501)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC501)
87
DVDD
—
Power supply terminal (+3.3 V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC501)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC501)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
Pin No.
Pin Name
I/O
Pin Description
33
ZS-M30
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6511FS (IC501)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6511FS (IC501)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6511FS (IC501)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6511FS (IC501)
95
FGIN
I (S)
96
TEST1
I
Input terminal for the test (fixed at “L”)
97
TEST2
I
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode
Pin No.
Pin Name
I/O
Pin Description
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
34
ZS-M30
1
LCD_DATA
—
Not used (OPEN)
2
LCD_CLK
—
Not used (OPEN)
3
LCD_CE
—
Not used (OPEN)
4
LCD_AO
—
Not used (OPEN)
5–7
—
Not used (OPEN)
8
BYTE
—
Not used (OPEN) (connect to ground)
9
CNVss
—
Ground terminal
10,11
—
Not used (OPEN)
12
SYS–RST
I
System reset input “L” reset
13
EXTAL
O
Main system clock output terminal (12MHz)
14
Vss
—
Ground terminal
15
XTAL
I
Main system clock input terminal (12MHz)
16
Vcc
—
Power supply terminal
17
—
Not used (fixed at “L” )
18
—
Not used (OPEN)
19
XINT
I
Sub system clock input terminal (32.768KHz)
20
PDOWN
I
Power down signal input from main system control (IC801)
21
—
Not used (OPEN)
22
LEO–0
—
Not used (OPEN)
23
LEO–1
—
Not used (OPEN)
24
LEO–2
—
Not used (OPEN)
25–30
—
Not used (OPEN)
31
SWDT
O
Writing data signal output to the serial bus
32
SRDT
I
Reading signal input from the serial bus
33
SCLK
O
Clock signal output to the serial bus
34
XLATCH
O
Latch signal output to the serial bus
35
TXD(UART)
I
Communication UART transfer input for main system control (IC801)
36
RXD(UART)
O
Communication UART receive output for main system control (IC801)
37
RTS(T)
I
UART transfer request input from master system control (IC801)
38
CTS(R)
O
UART transfer request output to master system control (IC801)
39,40
—
Not used (OPEN)
41
—
Not used (fixed at “L” )
42 – 45
—
Not used (OPEN)
46
—
Not used (fixed at “H” )
47– 50
—
Not used (OPEN)
51
A–MUTE
—
Not used (OPEN)
52
SDA
I/O
Serial data IN/OUT terminal for EEPROM (IC603)
53
SCL
O
Serial clock output terminal for EEPROM (IC603)
54
2654/2662
I
Destination select terminal
55
STB
O
Power ON/OFF control signal output
56
SCTX
O
Writing data transmission timing output to the CXD2654R (IC504)
shared with the magnetic head ON/OFF output
57
EMP
O
Diemphasis ON/OFF control signal output
58
DIG–RST
O
Reset signal output “L” reset
59
WRPWR
O
Write power ON/OFF output
60
DA–RST
O
Reset signal output to the D/A, A/D converter (IC604)
61
MOD
O
Laser modulation swithing signal output
62
Vcc
—
Power supply terminal
63
—
Not used (OPEN)
Pin No.
Pin Name
I/O
Pin Description
• MD BOARD IC601 MD System control ( M30620MCA-A73FP )
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