Sony ZS-D55 Service Manual ▷ View online
– 55 –
z
IC Block Diagrams (Main Section)
IC305 LA2010
IC301 TA2068N
23
22
21
4
5
6
3
2
1
20
24
7dB
LOGIC
ALC1
DET
26dB
15
16
17
9
8
7
10
11
12
18
19
14
13
7dB
ALC2
26dB
15k
6k
6k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
1k
1k
1k
1k
LINE
RADIO
RADIO
TAPE
TAPE
TAPE
LINE/IN-L
MIC
I/EX
TU-L
LINE/TU
TU-R
TAPE
LINE/IN-R
MIC
REC
OUT/L
OUT/R
VCC
LINE
TAPE
BUF AMP
A2
BUF AMP
B1
BUF AMP
B2
BUF AMP
A1
MIC
AMP1
MUTE
MUTE
MUTE
ON
ON
ON
NAB
AMP2
MONITOR
AMP
MONITOR
AMP
NAB
AMP1
REC
AMP2
REC
AMP1
REF AMP
2.1
L.PO
L.NF
L.RO
L.IN
R.IN
R.RO
R.NF
R.PO
MIC
NF
REF
GND
ALC
2
3
5
4
6
7
8
9
1
AMP
IN PUT
DET OUT
NF
TIME
GND
OUT PUT
VCC 2
GND
VCC 1
COMP(1)
COMP(2)
RESET
HOLD
– 56 –
IC701 CXA1992BR
z
IC Block Diagrams (CD Section)
Charge
up
FEO
FEI
FDFCT
FGD
FLB
FE_O
FE -
SRCH
TGU
TG2
FSET
TE-
TA-O
SL+
SL-
SLO
ISET
VCC
VCC
LOCK
CLK
XLT
DATA
XRST
C. OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
RFI
RFO
RF-M
RFTC
LD
PD
PD1
PD2
F. BIAS
F
E
EI
GND
TO
LPFI
TI
ATSC
TZC
VC
FZC
TM2
VEE
VEE
TM3
TM5
TM4
TM6
VCC
VCC
TM7
ISET
TTL
↓
IIL
IIL
↓
TTL
IIL
↓
TTL
IIL DATA REGISTER,
INPUT SHIFT REGISTER,
ADDRESS DECODER,
SENS SELECTOR,
OUTPUT DECODER
INPUT SHIFT REGISTER,
ADDRESS DECODER,
SENS SELECTOR,
OUTPUT DECODER
DFCTO IFB1-6
BAL1-4
TOG1-4
TOG1-4
FS1-4
TG1-2
TM1-7 PS1-4
FOH
FOL
TGH
TGL
BALH
BALL
ATSC
TZC
FZC
FSET
TG2
VEE
VCC
FS1
FS2
FOCUS
PHASE COMPENSATION
PHASE COMPENSATION
DFCT
FS4
TRACKING
PHASE COMPENSATION
PHASE COMPENSATION
TG1
TM1
DFCT
FZC COMP.
VEE
VCC
VCC
TDFCT
TZC COMP.
ATSC
WINDOW
COMP.
WINDOW
COMP.
E-F BALANCE
WINDOW COMP.
WINDOW COMP.
TRK. GAIN
WINDOW COMP.
WINDOW COMP.
FO. BIAS
WINDOW
COMP.
WINDOW
COMP.
VEE
TGFL
TOG1
TOG2
TOG3
TOG4
BAL1
BAL2
BAL3
BAL4
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
FE AMP
VEE
E IV AMP
F IV AMP
VCC
APC
VCC
VEE
LASER POWER CONTROL
VEE
PD1 IV
AMP
AMP
PD2 IV
AMP
AMP
RF
SUMMING
AMP
SUMMING
AMP
VCC
VEE
VEE
LEVEL S VEE
LEVEL S VEE
MIRR
VCC
DFCT
FOK
VCC
LDON
LPCL
LPC
TGFL
MIRR
DFCT1
CC1
1
2
3
4
5
6
7
8
9
10
11
12
13
26
39
40
41
42
43
44
45
46
47
48
49
50
51
52
38
37
36
35
34
33
32
31
30
29
28
27
24
24
23
22
21
20
19
18
17
16
15
14
– 57 –
IC702 CXD2589Q
CLOCK
GENERATOR
OSC
PWM
ASYMMETRY
CORRECTOR
DIGITAL
PLL
SERVO
AUTO
SEQUENCER
EFM
DEMODULATOR
SUB CODE
PROCESSOR
TIMING
LOGIC
CPU
INTERLACE
ERROR
CORRECTOR
16K
RAM
D/A
INTERFACE
DIGITAL
OUT
DIGITAL
CLV
SERIAL-IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd-ORDER
NOISE SHAPER
PWM
60
61
62
62
63
64
65
66
67
68
68
69
70
70
71
72
73
74
75
76
76
77
78
79
80
59 58 57
56
55
54 53 52 51 50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
22
21
VSS
LMUTE
RMUTE
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
XLON
FOK
VDD
VSS
MDP
PWMI
TEST0
TES1
VPCO1
VCKI
V16M
VCTL
PCO
FILO
FILI
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
LRCK
LRCKI
PCMD
PCMDI
BCK
BCKI
VSS
VDD
XUGF
XPCK
GFS
C2PO
XTSL
C4M
DOUT
EMPH
ENPHI
WFCK
SCOR
SBSO
EXCK
VSS
VDD
SYSM
AVSS
AVDD
AOUT1
AIN1
LOUT1
AVSS
XVDD
XTAI
XTAO
XVSS
AVSS
LOUT2
AIN2
AOUT2
AVDD
AVSS
XRST
VDD
– 58 –
IC790 BA6418N
3
4
5
6
7
9
1
8
T.S.D.
6.8K
20K
12K
20K
12K
6.8K
CONTROL LOGIC
DRIVER
GND
INPUT2
GND
NC
VCC
OUT1
GND
OUT2
INPUT1
2
IC703 BA6898FP
D
LEVEL SHIFT
27
28
26
25
24
23
2
1
3
4
5
6
7
8
9
10
11
12
13
14
LEVEL SHIFT
T. S. D.
REGULATOR, BIAS,
T. S. D. MONITOR
D
D
18
17
16
15
LEVEL SHIFT
D
22
D
D
LEVEL SHIFT
D
D
DRIVER
MUTE
VCC
21
20
19
VCC
GND
F-
F+
R+ FI
N
FIN
VREF
VCC
VCC
TIN
R+ TR
T-
T+
VREF
SPIN
SL-
SL+
SLIN
RST
REG –B
REGD
MUTE
GND
SPIN
R+ SP
SP-
SP+
GND
SPO
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