Sony XDR-S100CD Service Manual ▷ View online
XDR-S100CD
XDR-S100CD
33
33
4-15. SCHEMATIC DIAGRAM – JACK Section –
CN802
CN901
C236
C970
C480
R401
R402
R403
R404
TP401
TP403
TP402
TP404
R146
R145
R245
R246
CN304
C118
C219
C119
C218
C235
C234
C120
C220
C138
C238
CN801
CN808
C456
C457
C458
W802
S401
W806
W803
S402
W902
R125
R225
FB303
C237
C137
R244
R144
W303
W301
FB202
FB102
FB301
W302
J901
J303
SP101
SP201
F902
FH903
FH904
FH902
FH901
L901
J301
J302
F901
(Page 26)
(Page 27)
(Page 31)
(Page 31)
(Page 31)
(Page 31)
XDR-S100CD
XDR-S100CD
34
34
• IC Block Diagrams
IC101 CXD3059AR (BD81A Board)
IC251 BA5947FM-E2 (BD81A Board)
IC701 BA6956AN (DRIVER Board)
SERVO
INTERFACE
32
RFDCO
34
AC_SUM
35
EQ_IN
33
PDSENS
31
AVDD4
91
LMUT
92
NC
93
XTSL
94
IOVSS0
95
XTACN
96
SQSO
97
SQCK
98
SBSO
99
EXCK
1
MIRR
2
DFCT
3
FOK
9
SFDR
10
SRDR
11
TFDR
12
TRDR
13
FFDR
14
FRDR
19
E
20
F
26
A
27
B
28
C
29
D
30
NC
21
TEI
23
FEI
22
TEO
24
FEO
25
VC
5
LOCK
6
MDP
7
SSTP
4
VSS
8
IOVSS1
18
NC
15
IOVDD1
16
AVDD0
17
AVSS0
68 EMPH
66 BCK
67 VDD
71 DOUT
69 EMPHI
70 IOVDD2
64 VSS
63 LRCK
65 PCMD
75 NC
73 TES1
74 IOVSS2
78 XTAI
76 XVSS
79 XVDD
80 AVDD1
77 XTAO
72 TEST
MIRR
DFCT
FOK
TE
FE
SUM
PWM
GENERATOR
SERVO
DSP
A/D
CONVERTER
DC/DC
CONVERTER
ASYNMMETRY
CORRECTOR
SUB CODE
PROCESSOR
ERROR
CORRECTOR
32k
RAM
D/A
INTERFACE
D/A
COVERTER
SELECTOR
DIGITAL OUT
CPU INTERFACE
CLOCK
GENERATOR
SERVO
AUTO
SEQUENCER
LPF
LPF
DIGITAL
CLV
VC
ATT
39
RFC
EQ
41
RFACO
AMP
36
LD
37
PD
42
RFACI
43
AVDD3
44
BIAS
56
DDVRSEN
57
AVSS5
59
NC
54
AVDD5
58
DDCR
60
BCKI
55
DDVROUT
45
ASYI
47
VPCO
48
VCTL
49
AVSS3
46
ASYO
DIGITAL
PLL
EFM
DEMODULATOR
51
FILO
50
CLTV
52
FILI
53
PCO
38
NC
40
AVSS4
APC
112
XPCK
111
XUGF
110
WFCK
109
ATCK
101
SYSM
100
XRST
103
VSS
102
DATA
104
XLAT
106
VDD
107
SENS
105
CLOK
108
SCLK
113
GFS
116
VDD
115
SCOR
114
C2PO
117
C4M
119
COUT
118
WDCK
120
NC
82 VREFL
83 AVSS1
84 AVSS2
81 AOUT1
86 AOUT2
87 AVDD2
88 NC
89 IOVDD0
90 RMUT
85 VREFR
61 PCMDI
62 LRCKI
1
LEVEL SHIFT
MUTING
D
15
16
+ –
+
–
D
D
17
18
D
19
20
VREF
21
22
23
24
25
26
27
28
PREVCC
OPOUT
OUTVREF
CH4CAPA
CH4IN
CH3FIN
CH3RIN
GND
MUTE
POWVCC
CH3OUTF
CH3OUTR
CH4OUTF
CH4OUTR
OPIN–
2
OPIN+
INTERFACE
14
13
D
12
11
D
10
9
8
7
6
CH2FIN
CH2RIN
GND
5
4
CH1FIN
CH1RIN
VREFIN
POWVCC
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
INTERFACE
D
D
3
SW
INTERFACE
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
XDR-S100CD
35
START/STOP
DETECT CIRCUIT
HIGH VOLTAGE
GENERATOR
DATA OUTPUT/
ACK OUTPUT/
CONTROL CIRCUIAT
DATA
REGISTER
EEPROM
X DECODER
SELECTOR
DEVICE
ADDRESS
COMPARATOR
SERIAL CLOCK
CONTROL CIRCUIT
ADDRESS
COUNTER
Y DECODER
LOAD
COMP
LOAD
R/W
DOUT
DIN
A0
A1
A2
GND
INC
1
2
3
4
SDA
SCL
WP
VCC
5
6
7
8
IC802 S-24CS02AFT-TB-G (MAIN Board)
IC803 S-80828CNMC-B8NT2G (MAIN Board)
VREF
4
5
1
2
NC
NC
OUT
V
DD
3
V
SS
XDR-S100CD
36
IC301 BD3499FV-E2 (POWER AMP Board)
1
IN L1
18 BCB2 L
17 BCA1 L
16 BCA2 R
17 BCA1 L
16 BCA2 R
20 SB2 L
19 OUT2 R
22 SB1 L
21 SR
21 SR
24 VCC
23 OUT1 L
26 SDA
25 SCL
25 SCL
28 FIL
27 GND
27 GND
15 BCB2 R
2
IN R1
3
IN L2
5
IN L3
6
IN R3
4
IN R2
11
VOL1 L
12
VOL2 R
13
TG2 R
14
TG1 L
7
IN L4
8
IN R4
9
SEL2 R
10
SEL1 L
INPUT
SELECTOR
TREBLE/
BASS
INVERTER
VOLUME
INPUT
GAIN
SURROUND
PC BUS
LOGIC
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