Sony TAD-M30 Service Manual ▷ View online
— 29 —
Pin No.
1 to 10
11
12
13
14
15
16
17
18
19
20, 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 to 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55 to 60
61
62
63
64
65
66
67 to 80
I/O
—
—
I
O
O
O
O
O
O
O
—
I
O
O
O
O
I
—
—
—
—
I
I
—
—
—
—
—
—
O
O
O
O
O
O
—
I
O
—
—
—
I
—
—
—
—
—
Description
Not used (Connected to Ground)
Ground
Front/rear speaker select switch input (Front at H, Rear at L)
SURROUND ON/OFF display LED drive output
OPTICAL display LED drive output
COAXIAL display LED drive output
SET UP display LED drive output
Dolby display LED drive output
VOLUME UP data output
VOLUME DOWN data output
Not used (Connected to Ground)
STANDBY ON/OFF switch input
FL display clear output
FL display data output
FL display clock output
FL display latch output
Remote commander SIRCS signal input
Backup power supply +5 V
Non-backup power supply +5 V
Ground
Digital Ground
Key input, to A/D converter
Key input, to A/D converter
Digital Ground
Not used (Connected to Ground)
Not used (Connected to non-backup power supply +5 V)
Not used (Connected to non-backup power supply +5 V)
Not used (Connected to Ground)
Not used (Connected to non-backup power supply +5 V)
STOP signal output (to control microprocessor)
Reset signal output (to control microprocessor)
Slave request signal/data output (to control microprocessor)
Master request signal output (to control microprocessor)
Master data output (to control microprocessor)
Master clock output (to control microprocessor)
Ground
AUB power supply input
AUB power supply output
Ground
Not used (Connected to Ground)
Ground
Reset signal input
Digital Ground
External 4 MHz crystal oscillator for system clock is connected to this terminal
External 4 MHz crystal oscillator for system clock is connected to this terminal
Backup power supply +5 V
Not used (Connected to Ground)
Pin Name
—
VSS
FRONT/REAR
LED SURR
SED OPT
LED COAX
LED SETUP
LED DOLBY
VOL UP
VOL DOWN
—
STANDBY/ON
FLCLR
FLDATA
FLCLK
FLLATCH
SIRCS
AVCC
+AVREF
–AVREF
D GND
AD KEY1
AD KEY2
DVSS
—
MODE0
MODE1
MODE2
STANDBY
STOP
U-RST
U-SREQ
U-MREQ
U-DATA
U-CLK
GND
AUB IN
AUB OUT
GND
—
GND
RESET
DVSS
XO
XI
DVCC
—
3-13.
IC PIN FUNCTION DESCRIPTION
IC601 MB90673PF-G-264-BND (MODE CONTROL)/PANEL BOARD
— 30 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
—
O
O
O
O
—
O
—
—
—
O
O
O
O
—
O
—
O
O
O
—
O
O
O
O
I
I
—
—
I
—
I
—
—
I
I
I
I
I
—
Description
Address buffer Ground
Chip select 0 output to SRAM (Not used)
Chip select 3 output to SRAM (Not used)
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address bus buffer power supply (+5 V)
Address data output to SRAM (Not used)
Address bus buffer Ground
Power supply for internal logic (5 V)
Ground for internal logic
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address bus buffer Ground
Address data output to SRAM (Not used)
Address bus buffer power supply (+5 V)
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address bus buffer Ground
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
Address data output to SRAM (Not used)
SPI serial clock signal input from system controller
External frequency input (3 MHz)
Power supply for internal logic (5 V)
Ground for internal logic
PLL initialize input (Fixed to “L”)
Ground for PLL
PLL filter input (Connected to 0.01 uF capacitor)
Power supply for PLL (+5 V)
Ground for serial port
Master data input from system controller
Reset signal input from system controller
Mode select A (Fixed to “H”)
Mode select B (Fixed to “L”)
Mode select C (Fixed to “H”)
Power supply for serial port (+5 V)
Pin Name
AGND
MSC0
MSC3
MA14
MA13
AVCC
MA12
AGND
QVCC
QGND
MA11
MA10
MA9
MA8
AGND
MA7
AVCC
MA6
MA5
MA4
AGND
MA3
MA2
MA1
MA0
SCK
EXTAL
QVCC
QGND
PINIT
PGND
PCAP
PVCC
SGND
MISO
RESET
MODA
MODB
MODC
SVCC
IC118 DSP56009FJ88F (DIGITAL SIGNAL PROCESSOR)/MAIN BOARD
— 31 —
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
O
I
I
—
O
O
O
—
O
O
I
—
—
—
I
I
I
O
I
I
I
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
—
I/O
—
I/O
I/O
I/O
I/O
O
O
O
O
Description
Master data signal output to system controller
SPI slave select signal input from system controller
Host request signal input from system controller
Ground for serial port
Audio serial data 2 signal output (Not used)
Audio serial data 1 signal output
Audio serial data 0 signal output
Power supply for serial port (+5 V)
Serial clock transfer output
Word select transfer output
Serial clock reception input
Ground for internal logic
Power supply for internal logic (+5 V)
Ground for serial port
Word select reception
Audio serial data 1 signal input
Audio serial data 0 signal input
Debug serial signal output (Not used)
Debug serial signal input (Not used)
Debug serial clock signal input (Not used)
Debug request input (Fixed to “H”)
Data input/output with SRAM (Not used)
Data input/output with SRAM (Not used)
Data input/output with SRAM (Not used)
Data input/output with SRAM (Not used)
Ground for data bus buffer (+5 V)
Data input/output with SRAM (Not used)
Data input/output with SRAM (Not used)
Data input/output with SRAM (Not used)
Power supply for data bus buffer (+5 V)
Data input/output with SRAM (Not used)
Ground for data bus buffer
Input/output with general DIGITAL SIGNAL PROCESSOR (Not used)
Input/output with general DIGITAL SIGNAL PROCESSOR (Not used)
Input/output with general DIGITAL SIGNAL PROCESSOR (Not used)
Input/output with general DIGITAL SIGNAL PROCESSOR (Not used)
Write strobe signal output to SRAM (Not used)
Read strobe signal output to SRAM (Not used)
Low address strobe signal output to SRAM (Not used)
Column address strobe signal output to SRAM (Not used)
Pin Name
MOSI
SS
HREQ
SGND
SDO2
SDO1
SDO0
SVCC
SCKT
WST
SCKR
QGND
QVCC
SGND
WSR
SDI1
SDI0
DSO
DSI
DSCK
DR
MD7
MD6
MD5
MD4
DGND
MD3
MD2
MD1
DVCC
MD0
DGND
GPIO3
GPIO2
GPIO1
GPIO0
MRD
MWR
MRAS
MCAS
— 32 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
—
O
O
O
O
—
O
—
—
—
O
O
O
O
—
O
—
O
O
O
—
O
O
O
O
I
I
—
—
I
—
I
—
—
I
I
I
I
I
—
Description
Address buffer Ground
Chip select 0 output to SRAM (Not used)
Chip select 3 output to SRAM
Address data output to SRAM
Address data output to SRAM
Address bus buffer power supply (+5 V)
Address data output to SRAM
Address bus buffer Ground
Power supply for internal logic (5 V)
Ground for internal logic
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Address bus buffer Ground
Address data output to SRAM
Address bus buffer power supply (+5 V)
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Address bus buffer Ground
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
SPI serial clock signal input from system controller
External frequency input (3 MHz)
Power supply for internal logic (5 V)
Ground for internal logic
PLL initialize input (Fixed to “L”)
Ground for PLL
PLL filter input (Connected to 0.01 uF capacitor)
Power supply for PLL (+5 V)
Ground for serial port
Master data input from system controller
Reset signal input from system controller
Mode select A (Fixed to “H”)
Mode select B (Fixed to “L”)
Mode select C (Fixed to “H”)
Power supply for serial port (+5 V)
Pin Name
AGND
MSC0
MSC3
MA14
MA13
AVCC
MA12
AGND
QVCC
QGND
MA11
MA10
MA9
MA8
AGND
MA7
AVCC
MA6
MA5
MA4
AGND
MA3
MA2
MA1
MA0
SCK
EXTAL
QVCC
QGND
PINIT
PGND
PCAP
PVCC
SGND
MISO
RESET
MODA
MODB
MODC
SVCC
IC119 SSP424023FJ88 (DIGITAL SIGNAL PROCESSOR)/MAIN BOARD
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