Sony TA-VA777ES / VUCD-777A Service Manual ▷ View online
45
9
S5
S6
S7
S4
S1
S2
S3
Vout1
Vout2
Vout3
V-
GND
SW3
SW2
SW1
SW5
SW4
Vin1
Vin2
Vin3
Vin4
Vin5
V+
10
11
12
13
14
15
16
1
5
2
3
4
6
7
8
PROTECTOR
DRIVE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
PRE
DRIVE
PRE
DRIVE
BIAS CIRCUIT
REG
MUTE
+VOUT1
–
VOUT1
COMP1
NF1
IN1
GND
IN2
NF2
COMP2
–
VOUT2
+VOUT2
VCC1
VCC2
VEE
DRIVE
1
5
2
7
3
6
4
POWER
AMP.
AMP.
POWER
AMP.
AMP.
CONTROL
INPUT
AMP.
INPUT
AMP.
REG
8
VCC
VCC
REFERENCE
OUT2
OUT1
IN1
IN2
GND
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Q
A
Q
B
Q
C
Q
D
A
CLEAR
VCC
Q
A
Q
B
Q
C
Q
D
A
CLEAR
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
INRP
INRM
REFI
AVDD
AVSS
APD
NU
NU
TEST1
LRCK1
BCK1
ADDT
V35A
VSS1 (LF)
MCKI
DPD
VSS2(LF)
INIT
MODE
SHIFT
LATCH
256CK
V35D
VSS2
512CK
BCK2
DADT
LRCK2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INLP
INLM
REFO
LVSS
LVDD
AVSS(LF)
NU
NU
VSS1(LF)
TEST3
TEST2
VSS1
VDD1
VDD1
VDD2
L1
AVDDL
L2
AVSSL
XVSS
XIN
XOUT
XVDD
AVSSR
R2
AVDDR
R1
VDD2
MODULATOR
MODULATOR
DECIMATION
FILTER
DECIMATION
FILTER
LOW CUT
FILTER
LOW CUT
FILTER
VOLTAGE
REFERENCE
I/O
I/O
ATT
PLM
OVER
SAMP
FILTER
NOISE
SHAPER
CPU
INTERFACE
+
–
+
–
ATT
PLM
OVER
SAMP
FILTER
NOISE
SHAPER
IC5201, 5202 NJM2296 (S VIDEO board)
IC5101 NJM2296 (C VIDEO board)
IC5101 NJM2296 (C VIDEO board)
IC4101, 4201, µPC2581v (AMP board)
IC101 M54641L (DISPLAY board)
IC336, 362 TC74HC393A (DIGITAL board)
IC307 CXD8607N (DIGITAL board)
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
I/F
SERIAL
IN
I/F
X'TAL
OSC
POWER
MODE
CONTROL
I/F
MULTI FUNCTION
EIGHT MULTIPLE
OVER SAMPLING
OVER SAMPLING
DIGITAL FILTER
(SYSTEM CLOCK)
LRCIN
SRO
BCKO
WCKO
DOL
DOR
VDD
NC
OW1
OW0
SF1
SF0
DEM
MUTE
DIN
BCKIN
IIS
IW0
IW1
XTI
XTO
VSS
CLKO
MODE
MD/CKO
MC/LRIP
RST
ML/RESV
1
2
3
4
5
6
7
8
9
NC
OUTPUT 2
Vcc
GND
NC
INPUT 2
INPUT 1
NC
MOTOR
DRIVE
MOTOR
DRIVE
REG
SWITCH
SWITCH
OUTPUT1
1
3
4
5
11
10
12
9
C1+
C1-
C2+
C2-
T1 IN
T2 IN
R1 OUT
R2 OUT
T1
T2
R2
R1
16
2
6
14
7
13
8
15
VCC
V+
V-
T1 OUT
T2 OUT
R1 IN
R2 IN
GND
+5V TO +10V
VOLTAGE
DOUBLER
+10V TO -10V
VOLTAGE
DOUBLER
IC338, 339, 340 DF1704E (DIGITAL board)
IC333 BA6208F (DIGITAL board)
IC1601 ADM202EARN (CTRL A1 board)
47
3-39. IC PIN FUNCTION DESCRIPTION
IC347, 348 CXD2712R AUDIO DSP(DIGITAL BOARD)
Pin No.
1
2 – 5
6, 7
8
9
10
11
12
13
14
15
16 – 20
21
22
23 – 25
26
27 – 30
31
32 – 40
41
42
43 – 49
50
51
52
53 – 60
61
62 – 69
70
71
72
73
74
75
76 – 80
81
82
83 –89
90
I/O
—
O
I
NC
I
I
—
—
O
I
I
I/O
—
—
I/O
I
O
—
I/O
—
—
I/O
I
—
—
I/O
—
I/O
O
—
—
O
O
O
I/O
—
—
I/O
O
Description
Ground
Serial data output
Conditional jump input terminal (7pin Connected to ground)
No connection
HCIF data write
HCIF data read
Ground
+3.3V
HCIF ready signal Open drain
HCIF chip select
HCIF address input
HCIF data input/output
Ground
+3.3V
HCIF data input/output
Reset input “L”: active
Test data output
Ground
External RAM data input/output
Ground
+3.3V
External RAM data input/output
Test data input “L” = normal “H” = test (Connected to ground)
Ground
+3.3V
External RAM data input/output
Ground
External RAM data input/output
External RAM output enable
Ground
+3.3V
External RAM column address strobe (Not used)
External RAM write enable (Not used)
External RAM raw address strobe
External RAM address output/test data input
Ground
+3.3V
External RAM address output/test data input
External RAM address output
Pin Name
VSS3
SOA – SOD
ECJ0, ECJ1
—
XHDWR
XHDRD
V
SS
4
V
DD
2
HRDY
XHDCS
HA0
HD0 – HD4
V
SS
5
V
DD
3
HD5 – HD7
XRST
FGP0 – FGP3
V
SS
6
ED0 – ED8
V
SS
7
V
DD
4
ED9 – ED15
TSTD
V
SS
8
V
DD
5
ED16 – ED23
V
SS
9
ED24 – ED31
XOE
V
SS
10
V
DD
6
CAS
XWE
RAS
EA0 – EA4
V
SS
11
V
DD
7
EA5 – EA11
EA12
48
Pin No.
91
92 – 94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117 – 120
I/O
—
O
O
I
I
O
I
O
—
—
—
—
I/O
I
I
I
O
O
—
—
I
I
I
I
I
Description
Ground
External RAM address output
Not used
Test data input “L” = normal “H” = test (Connecting to ground)
PLL input frequency select “L” = 256Fs “H” = 128Fs (Connecting to ground)
PLL output frequency select “L” = 768Fs “H” = 1024Fs (Connecting to ground)
Master clock input
Master clock output (Not used)
Ground
+3.3V
Ground for PLL cell
VDD for PLL cell
PLL output/test clock input
PLL cell oscillation enable “L” oscillation enable “H” oscillation stop (Connecting to ground)
Test data input “L” = normal “H” = test (Connecting to ground)
Frequency counter input (Connecting to ground)
LRCK0 divider output
BCK0 divider output
Ground
+3.3V
BCK input
BCK input
LRCK input
LRCK input
Serial data input
Pin Name
V
SS
0
EA13 – EA15
EA16
TSTA
PLDIVF
PLDIVB
CLKI
CLKO
V
SS
1
V
DD
0
AV
SS
AV
DD
PLLCK
XPLLEN
TST
LRCT
LROUT
BKOUT
V
SS
2
V
DD
1
BCK0
BCK1
LRCK0
LRCK1
SIA – SID
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