Sony TA-E9000ES Service Manual ▷ View online
TA-E9000ES
– 93 –
– 94 –
4-27. SCHEMATIC DIAGRAM – AC INPUT SECTION –
• See page 95 for Printed Wiring Board.
(Page 89)
(Page 89)
(Page 63)
TA-E9000ES
– 95 –
– 96 –
4-28. PRINTED WIRING BOARD – AC INPUT SECTION –
• See page 12 for Circuit Boards Location.
(Page 92)
(Page 92)
(Page 60)
– 97 –
(Page 59)
(Page 60)
(Page 60)
4-30. PRINTED WIRING BOARD – CLOCK SECTION –
• See page 12 for Circuit Boards Location.
4-29. SCHEMATIC DIAGRAM – CLOCK SECTION –
(Page 75)
(Page 75)
(Page 76)
TA-E9000ES
– 98 –
4-31. IC BLOCK DIAGRAMS
• VIDEO section
IC201 MC14051BCP
1
2
3
4
5
6
7
8
X4
X6
X7
X5
INH
VEE
VSS
VDD
X2
X0
X7
X3
A
B
C
COM
9
10
11
12
13
14
15
16
IC204 uPD4053BC
1
2
3
4
5
6
7
8
B1
B0
C.COM
CO
INH
VEE
VSS
VDD
B.COM
A.COM
A1
A0
A
B
C
C1
9
10
11
12
13
14
15
16
OPEN
OPEN
OPEN
IC207 MC14066BCP
1
IN/OUT
7
V
SS
6
CONTROL IN
5
CONTROL IN
4
IN/OUT
3
OUT/IN
2
OUT/IN
8
IN/OUT
14 V
DD
13 CONTROL IN
12 CONTROL IN
11 IN/OUT
10 OUT/IN
9
OUT/IN
• ANALOG section
IC502 LC7822
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CONTROL
LATCH
SHIFT RESISTOR
LEVEL SHIFT
CL
DI
CE
VEE
OUT
IN
OUT
IN
OUT
IN
VSS
S
RESET
VDD
OUT
IN
IN
OUT
IN
OUT
IN
IC524 MC74HC595AF
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
SHIFT REGISTER
LATCH
PARALLEL DATA
OUTPUT
GND
VCC
LATCH
CLOCK
PARALLEL DATA
OUTPUT
SERIAL DATA
INPUT
OUTPUT
ENABLE
SHIFT
CLOCK
SERIAL DATA
OUTPUT
RESET
QB
QC
QD
QE
QF
QG
QH
SQH
A
QA
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