Sony STR-SL50 Service Manual ▷ View online
17
STR-SL50
3-11. IC Pin Function Descriptions
• IC1201 CXD9617R (AUDIO DSP) (DIGITAL BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 to 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
—
I
I
I
—
I
O
—
—
—
—
—
I
O
I/O
—
I/O
I
O
O
—
I/O
O
O
O
I
I
I
—
O
I
I
O
I
O
O
O
—
—
O
O
O
O
—
I
—
I
O
—
O
Pin Name
VSS
XRST
EXTIN
FS2
VDD1
FS1
PLOCK
VSS
MCLK1
VDDI
VSS
MCLK2
MS
SCKOUT
LRCKI1
VDDE
BCKI1
SDI1
LRCKO
BCKO
VSS
KFSIO
SDO1 to SDO3
SDO4
SPDIF
LRCKI2
BCKI2
SDI2
VSS
HACN
HDIN
HCLK
HDOUT
HCS
SDCLK
CLKEN
RAS
VDDI
VSS
CAS
DQM/OE0
CS0
WE0
VDDE
WMD1
VSS
WMD0
PAGE2
VSS
PAGE1
Description
Ground terminal
Rest input from the system control
Not used (connected to the ground)
Not used (connected to the ground)
Power supply terminal (+2.5V)
Not used (connected to the ground)
Internal PLL lock signal output Not used (open)
Ground terminal
Resonator terminal (13.5MHz)
Power supply terminal (+2.5V)
Ground terminal
Resonator terminal (13.5MHz)
Master/slave operation selection terminal (L : internal clock) (fixed at “L”)
Internal system clock output to the CODEC (IC1501)
Not used (open)
Power supply terminal (+3.3V)
Bit clock input-output terminal for audio interface serial data Not used (open)
Data input from the CODEC (IC1501)
Sampling clock output to the CODEC (IC1501)
Bit clock output to the CODEC (IC1501)
Ground terminal
Audio clock (384fs/256fs) input from the DIR (IC1101)
Serial data output to the CODEC (IC1501)
Serial data output terminal Not used (open)
SPDIF power output terminal Not used (open)
Sampling clock input to the DIR (IC1101)
Bit clock input from the DIR (IC1101)
Data input from the DIR (IC1101)
Ground terminal
Acknowledge signal output to the system control (IC1601)
Serial data input from the system control (IC1601)
Clock input from the system control (IC1601)
Serial data output to the system control (IC1601)
Chip select signal input from the system control (IC1601)
SDRAM clock Not used (open)
SDRAM clock enable Not used (open)
Row address strobing Not used (open)
Power supply terminal (+2.5V)
Ground terminal
Column address strobing Not used (open)
Data I/O mask Not used (open)
Chip select signal output to the SRAM (IC1202)
Write enable signal output to the SRAM (IC1202)
Power supply terminal (+3.3V)
Setting WAIT mode for external memory (pull up)
Ground terminal
Setting WAIT mode for external memory (pull up)
External memory page switch signal output Not used (open)
Ground terminal
External memory page switch signal output Not used (open)
18
STR-SL50
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64 to 66
67
68
69
70
71
72 to 75
76
77 to 80
81
82 to 85
86
87
88
89
90
91
92 to 97
98,99
100
101
102 to 105
106
107,108
109,110
111
112
113
114
115
116
117 to 119
120
Pin Name
PAGE0
BOOT
BTACT
BST
MOD1
MOD0
EXLOCK
VDDI
VSS
A17
A16
A15 to A13
GP10
GP9
GP8
VDDI
VSS
D15/GP7 to D12/GP4
VDDE
D11/GP3 to D8/GP0
VSS
A9 to A10
TDO
TMS
XTRST
TCK
TDI
VSS
A8 to A3
D7,D6
VDDI
VSS
D5 to D2
VDDE
D1,D0
A2,A1
VSS
A0
PM
SD13
SD14
SYNC
VSS
VDDI
I/O
O
I
O
I
I
I
I
—
—
O
O
O
O
O
I
—
—
I/O
—
I/O
—
O
O
I
I
I
I
—
O
I/O
—
—
I/O
—
I/O
O
—
O
I
I
I
I
—
—
Description
External memory page switch signal output Not used (open)
Not used (connected to the ground)
Boot mode status display signal Not used (open)
Boot strap signal input from the system control (IC1601)
Setting for 256fs (pllx9) (pull up)
Setting for single chip mode (pull down)
Lock signal input terminal
Power supply terminal (+2.5V)
Ground terminal
External memory address Not used (open)
External memory address Not used (open)
Address signal output to the SRAM (IC1202)
LRCK0 signal output
GP9 (DECODE) signal output to the system control (IC1601)
GP8 (AUDIO) signal input from the DIR (IC1101)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
Simple emulation data output Not used (open)
Simple emulation data entry beginning and the end terminal Not used (open)
Asynchronous simple BREAK input terminal of emulation Not used (open)
Simple emulation clock input Not used (open)
Simple emulation data entry Not used (open)
Ground terminal
Address signal output to the SRAM (IC1202)
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1202)
Address signal output to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
PLL initialization signal input from the system control (IC1601)
Data entry terminal Not used (open)
Data entry terminal Not used (open)
Synchronization / asynchronous selection terminal (L:Sync. H:Async.) (fixed at “H”)
Ground terminal
Power supply terminal (+2.5V)
19
STR-SL50
• IC1601 MB90478PF-G-139-BND (SYSTEM CONTROL)(DIGITAL BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 to 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
I
I
O
O
I
O
O
O
O
O
—
O
O
O
O
O
O
I
O
O
O
O
—
O
I
O
I
I
O
I
O
I/O
—
—
—
I
I
I
I
—
I
I
I
I
I
I
I
I
I
I
Pin Name
DATA O
GP9
BST
HCS
HACN
XRST
PM
PD
SMUTE
CDT1
VSS
SCL
CS
DATA
CLK
LATCH
WOOFER RELAY
HDOUT
HDIN
HCLK
F.MUTE
VIDEO-SW1
VCC5
ANA/DIG
NOT IN USE
VIDEO-SW2
FLASH2
FLASH1
VIDEO-MUTE
NC
SCL
SDA
AVCC
AVRH
AVSS
A/D0
A/D1
A/D2
A/D3
VSS
RDS SIGNAL
MODEL
VERSION
NC
CRYSTAL SEL
STOP
MD0
MD1
MD2
RDS CLK
Description
Data input from the DIR (IC1101)
External memory data input from the DSP (IC1201)
Boot strap signal output to the DSP (IC1201)
Chip select signal output to the DSP (IC1201)
Acknowledge signal input from the DSP (IC1201)
Reset signal output to the DSP (IC1201)
PLL initialization signal output to the DSP (IC1201)
Power down signal output to the CODEC (IC1501)
Soft mute signal output to the CODEC (IC1501)
Control data output to the CODEC (IC1501)
Ground terminal
Serial clock output to the CODEC (IC1501)
Chip select signal output to the CODEC (IC1501)
Serial control data output to the tuner and the IC401
Serial control clock output to the tuner and the IC401
Latch signal output to the IC401
Sub woofer relay control signal output
Serial data input from the DSP (IC1201)
Serial data output to the DSP (IC1201)
Clock signal output to the DSP (IC1201)
Function mute signal output
Video switch signal output to the video switch (IC201)
Power supply terminal (+3.3V) (STBY)
Function mute and error port signal output
Not used (fiexed at “L”)
Video switch signal output to the video switch (IC201)
Flash programming input
Flash programming input
Video mute signal output to tthe video switch (IC201)
Not used (fixed at “L”)
Clock output to the EEPROM (IC1604)
Serial data input/output from/to the EEPROM (IC1604)
Power supply terminal (A/D converter) (+3.3V)
External reference power supply (A/D converter)
Ground terminal (A/D converter)
Not used (fixed at “L”)
Key data signal input from S113, 116
Key data signal input from S111, 112
Key data signal input from S114, 115
Ground terminal
RDS signal level input
Model setting terminal
Destination setting terminal
Not used (fixed at “L”)
Not used (fixed at “L”)
Power stop detection signal input
Flash programming MD0 input
Operation mode setting terminal
Flash programming MD2 input
RDS clock input from the tuner
20
STR-SL50
Pin No.
53
54
55
56
57, 58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87 to 92
93
94
95
96
97
98
99
100
Pin Name
RDS DATA
SIRCS
FUSE DETECT
POWER KEY
NOT IN USE
VOL(B)
VOL(A)
DIN
CLK
FL_STB
FAN_ON
FAN_CLK
POWER RELAY
PROTECTOR
F_CTRL2
F_CTRL1
REAR RELAY
CENTER RELAY
FRONT RELAY
TUNED
STEREO
MUTE
DO
RSTX
SLATCH
X1A
X0A
VSS
X0
X1
VCC3
NOT IN USE
NC
NOT IN USE
XMODE
CKSEL1
CLK
CE
DI
DO
ERROR
XSTATE
I/O
I
I
I
I
I
I
I
O
O
O
I
I
O
I
O
O
O
O
O
I
I
O
I
I
O
—
—
—
I
O
—
I
I
I
O
O
O
O
O
I
I
I
Description
RDS data input from the tuner
Data input from the remote control receiver
Fuse open detection signal input
Power switch detection signal input
Not used (fixed at “L”)
Volume signal input from the rotary encoder
Volume signal input from the rotary encoder
Serial control data output to the FL/LED driver (IC152)
Clock signal output to the FL/LED driver (IC152)
Latch signal output to the FL/LED driver (IC152)
Fan on level detection signal input
Feedback signal input from the fan (FAN901)
Power relay drive signal output
Protect detection signal input
Fan speed control signal output
Fan ON/OFF control signal output
Surround speasker relay control signal output
Center speasker relay control signal output
Front speasker relay control signal output
Tuning a frequency detection signal input from the tuner
Stereo detection signal from the tuner
Muting control signal output to the tuner
Data input from the tuner
System reset input
Serial control latch signal output to the tuner
Not used (open)
Not used (connected to the ground)
Ground terminal
Terminal for a oscillator
Terminal for a oscillator
Power supply terminal (+3.3V) (STBY)
Not used (fixed at “L”)
Not used (fixed at “L”)
Not used (fixed at “L”)
Reset signal output to the DIR (IC1101)
Clock selection signal output to the DIR (IC1101)
Clock output to the DIR (IC1101)
Chip enable signal output to the DIR (IC1101)
Data output to the DIR (IC1101)
Data input from the DIR (IC1101)
PLL lock error, data error flag input from the DIR (IC1101)
XSTATE signal input from the DIR (IC1101)
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