Sony STR-MD777 Service Manual ▷ View online
STR-MD777
– 53 –
– 54 –
4-24. SCHEMATIC DIAGRAM – EDIT FL Board –
•
See page 16 for Waveforms.
•
See page 59 for IC Block Diagrams.
(Page 26)
(Page 46)
(Page 49)
(Page 49)
(Page 49)
STR-MD777
– 55 –
– 56 –
4-25. PRINTED WIRING BOARDS – SUB POWER/TA PRIMARY/TA SECONDARY Boards –
•
See page 10 for Circuit Boards Location.
Ref. No.
Location
Ref. No.
Location
D901
C-2
D902
C-1
D904
B-1
D905
C-2
D906
C-2
D907
C-2
D908
C-2
D909
C-3
D910
C-3
D911
B-3
D912
A-3
• Semiconductor Location
D913
A-3
D914
B-2
IC901
B-2
Q902
B-2
Q903
B-2
Q904
A-2
Q905
A-1
Q906
B-1
Q907
B-1
VOLTAGE
SELECTOR
S901
110-120V 220-240V
SUB POWER BOARD
SUB POWER
TRANSFORMER
TA PRIMARY BOARD
TA SECONDARY BOARD
MAIN POWER
TRANSFORMER
(Page 27)
(Page 56)
(Page 17)
(Page 17)
(Page 55)
STR-MD777
– 57 –
– 58 –
4-26. SCHEMATIC DIAGRAM – SUB POWER/TA PRIMARY/TA SECONDARY Boards –
(Page
26)
(Page
22)
(Page
21)
• IC Block Diagrams
IC141, 142
P82B715PN (MAIN Board)
IC501
BA3833F-E2 (MAIN Board)
IC601
M66004M8FP (STR FL Board)
IC604
M66004M8FP (EDIT FL Board)
IC302
µPC1237HA (MAIN Board)
IC603
NJU3718G (TU) (FUNCTION Board)
IC605
NJU3718G (TU) (EDIT FL Board)
GND
NC
NC
VCC
LCL
SCL
SDA
LDA
BUFFER
BUFFER
1
5
2
8
7
6
3
4
1
2
3
4
5
6
7
8
OVER LOAD DET
F/F
OFFSET DET
LATCH/
AUTORESET
V
CC
ON
MUTE
AC OFF
DET
V
CC
2
3
14
1
f04
13 f
12 VCC
11 NC
10 NC
15 f03
5
GND
6
BIAS
C
7
NC
8
NC
9
NC
4
16 f02
17 f01
18 RESET
RESET
C
PREF
LINE
NF
LINE
IN
REFFERENCE
CURRENT
BPF
DET
BPF
DET
BPF
DET
BPF
DET
DET
RESET
Bias
INDICATION
CODE
RESISTOR
(8BIT x 16)
DECODER
(35BIT x 16)
DECODER
(35BIT x 16)
CODE/COMMAND
CONTROL
CIRCUIT
INDICATION
CONTROL
RESISTOR
INDICATION
CONTROLLER
DIGITAL
OUTPUT
CIRCUIT
OUTPUT
CIRCUIT
CODE
WRITE
SERIAL
RECEIVE
CIRCUIT
OUTPUT
PORT
(2BIT)
CLOCK
GENERATOR
CIRCUIT
RAM WRITE
CODE SELECT
DIG12
|
DIG15
V
CC
2
SEG0
|
SEG26
V
SS
XIN
XOUT
V
CC
1
RES
DIG11
|
DIG0
CS
CLK
DATA
SEG35
|
SEG27
P1
P0
14
15
16
17
18
19
20
21
22
23
|
31
13
1
|
12
SEGMENT OUTPUT CIRCUIT
59
|
33
60
32
VP
64
|
61
1
28
2
3
4
5
6
7
8
9
10
12
11
PARALLEL
DATA
OUTPUT
BUFFER
LATCH
CIRCUIT
SHIFT
REGISTER
SERIAL
DATA
OUTPUT
BUFFER
CONTROL
CIRCUIT
18
17
14
15
16
19
20
21
22
23
24
25
26
27
P9
P10
P11
P12
P13
P13
P14
VSS
P15
P16
P17
P18
P19
P20
SO
VDD
P8
P7
P6
P5
P4
P3
VSS
P2
P1
CLR
STB
CLK
DATA
13
– 59 –
– 60 –
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