Sony STR-LV500 Service Manual ▷ View online
9
STR-LV500
4-1. IC Pin Function Descriptions
• IC115 CXD9617R (AUDIO DSP) (DIGITAL BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 to 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
—
I
I
I
—
I
O
—
I
—
—
O
I
O
I
—
I
I
O
O
—
I
O
O
O
I
I
I
—
O
I
I
O
I
O
O
O
—
—
O
O
O
O
—
I
—
I
O
—
O
Pin Name
VSS
XRST
EXTIN
FS2
VDD1
FS1
PLOCK
VSS
MCLK1
VDD1
VSS
MCLK2
MS
SCKOUT
LRCKI1
VDDE
BCKI1
SDI1
LRCKO
BCKO
VSS
KFSIO
SDO1 to SDO3
SDO4
SPDIF
LRCKI2
BCKI2
SDI2
VSS
HACN
HDIN
HCLK
HDOUT
HCS
SDCLK
CLKEN
RAS
VDDI
VSS
CAS
DQM/OE0
CSO
WEO
VDDE
WMD1
VSS
WMD0
PAGE2
VSS
PAGE1
Description
Ground terminal
Rest input from the system control
Not used (connected to ground)
Not used (connected to ground)
Power supply (+2.5V)
Not used (connected to ground)
Not used (open)
Ground terminal
Clock input (13.5MHz)
Power supply (+2.5V)
Ground terminal
Clock output (13.5MHz)
Not used (connected to ground)
Internal system clock output to AK4527B
Not used (open)
Power supply (+3.3V)
Not used (open)
Serial data input from AK4527B
Sampling clock output to AK4527B
Bit clock output to AK4527B
Ground
Audio clock (384fs/256fs) input from LC89056W
Serial data output to AK4527B
Not used (open)
Not used (open)
Sampling clock input from LC89056W
Bit clock input from LC89056W
Serial data input from LC89056W
Ground
Acknowledge output to MB90478
Serial data input from MB90478
Clock input from MB90478
Serial data output to MB90478
Chip selection input from MB90478
Not used (open)
Not used (open)
Not used (open)
Power supply (+2.5V)
Ground
Not used (open)
Not used (open)
Chip selection output to the SRAM
Write enable output to the SRAM
Power supply (+3.3V)
Not used (connected to ground)
Ground
Not used (connected to VDD)
Not used (open)
Ground
Not used (open)
SECTION 4
DIAGRAMS
10
STR-LV500
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64 to 66
67 to 69
70
71
72 to 75
76
77 to 80
81
82 to 85
86
87
88
89
90
91
92 to 97
98,99
100
101
102 to 105
106
107,108
109,110
111
112
113
114
115
116
117 to 119
120
Pin Name
PAGE0
BOOT
BTACT
BST
MOD1
MOD0
EXLOCK
VDDI
VSS
A17
A16
A15 to A13
GP10 to GP8
VDDI
VSS
D15/GP7 to D12/GP4
VDDE
D11/GP3 to D8/GP8
VSS
A9 to A10
TDO
TMS
XTRST
TCK
TDI
VSS
A8 to A3
D7,D6
VDDI
VSS
D5 to D2
VDDE
D1,D0
A2,A1
VSS
A0
PM
SD13
SD14
SYNC
VSS
VDDI
I/O
O
I
O
I
I
I
I
—
—
O
O
O
I/O
—
—
I/O
—
I/O
—
O
O
I
I
I
I
—
O
I/O
—
—
I/O
—
I/O
O
—
O
I
I
I
I
—
—
Description
Not used (open)
Not used (connected to ground)
Not used (open)
Boot strap signal input from MB90478
Mode input (connected to VDD)
Mode input (connected to ground)
Lock signal input to LC89056W
Power supply (+2.5V)
Ground
Not used (open)
Not used (open)
Address bus output to the SRAM
External memory data I/O general purpose port terminal GP
Power supply (+2.5V)
Ground
SRAM data bus
Power supply (+3.3V)
SRAM data bus
Ground
Address bus output to the SRAM
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Ground
Address bus output to the SRAM
SRAM data bus
Power supply (+2.5V)
Ground
SRAM data bus
Power supply (+3.3V)
SRAM data bus
Address bus output to the SRAM
Ground
Address bus output to the SRAM
PLL initialization input from MB90478
Not used (open)
Not used (open)
Synchronization / asynchronous selection input (pull up)
Ground
Power supply (+2.5V)
11
STR-LV500
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I
I
O
O
I
O
O
O
O
O
—
O
—
O
O
O
O
I
O
O
O
O
—
O
I
O
I
—
—
I
I
I
O
I/O
—
I
—
I
I
O
I
—
—
I
I
I
I
I
I
I
Pin Name
DATA O
GP9
BST
HCS
HACN
XRST
PM
VCONT
PD
PWCONT2
VSS
PWCONT1
NC
DATA
CLK
WOOFER RELAY
HEADPONE RELAY
HDOUT
HDIN
HCLK
POWER KEY OUT
VIDEO-SWA
VCC5
VIDEO SW C
HP DETECT
VIDEO SWB
FLASH2
NC
NC
NC
NC
NC
SCL
SDA
AVCC
AVRH
AVSS
A/D0
A/D1
FM SIG OUT
A/D3
VSS
NC
MODEL
VERSION
NC
CRYSTAL SEL
STOP
MD0
MD1
Description
Serial data input from LC89056W
External memory data input from CXD9617R
Boot strap signal output to CXD9617R
Chip selection signal output to CXD9617R
Acknowledge signal input from CXD9617R
Reset signal output to CXD9617R
PLL initialization signal output to CXD9617R
Power voltage control
PD signal output to AK4527B
IC903, 907 On/Off control
Ground
Power control
Not used (Pull down)
Serial control data output to the tuner and M61527FP
Serial control clock output to the tuner and M61527FP
Sub woofer relay control signal output
Headphone relay control signal output
Serial data input from CXD9617R
Serial data output to CXD9617R
Clock signal output to CXD9617R
Not used
Video switch signal output to the NJM2279
Power supply (+3.3V (STBY))
Video switch signal output to the NJM2279
Detects headphone switch On/Off
Video switch signal output to NJM2279
Flash programming input
Not used (pull down)
Not used (pull down)
Not used (pull down)
Not used (pull down)
Not used (pull down)
SCL signal output to the EEPROM
SDA signal from the EEPROM
Power supply (+3.3V(STBY))
A Vref input (connected to +3.3 (STBY))
Ground
Not used (pull down)
Key signal input
FM antenna input level
Key signal input
Ground
Not used (pull down)
Model detection input
Version resisrtor input
Not used (pull down)
Not used (pull down)
AC off signal input
Flash programming MD0 input
Not used (connected to +3.3V(STBY))
• IC118 MB90478PF-G-149-BND (SYSTEM CONTROL) (DIGITAL BOARD)
12
STR-LV500
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
MD2
RDS INT
RDS DATA
SIRCS
DIAG
POWER KEY
NOT IN USE
NOT IN USE
SCDT
SHIFT
DIN
CLK
FL_STB
FAN_ON
FAN_CLK
VOL(B)
VOL(A)
TC74153H B
TC74153H A
NJU4066
TC4052A
TC4052B
TUNED
STEREO
MUTE
DO
RSTX
SLATCH
X1A
X0A
VSS
XO
XI
VCC3
RST
NSMUTE
NC
NC
LAT3
LAT2
LAT1
EN
XMODE
CKSEL1
CLK
CE
DI
DO
ERROR
XSTATE
I/O
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
O
O
O
O
O
I
I
O
I
I
O
—
—
—
O
I
—
O
O
I
I
O
O
O
O
O
O
O
O
O
I
I
I
Description
Flash programming MD2 input
RDS clock input to tuner
RDS data input to tuner
Data input from the remote control receiver
Protect
Power swich detection signal input
Not used (pull down)
Not used (pull down)
IC405, 408, 411 control
IC405, 408, 411 control
Serial data output to
µPD16315
Clock signal output to
µPD16315
STB signal output to
µPD16315
Fan motor on detection signal input
Feedback signal input from fan motor
Volume signal input from the rotary encoder
Volume signal input from the rotary encoder
IC105 control (Digital input select switch)
IC105 control (Digital input select switch)
IC106 control (Analog input select switch)
IC108 control (Analog input select switch)
IC108 control (Analog input select switch)
Tuning a frequency detection signal input from the tuner
STEREO tuning signal from the tuner
Muting control signal output from the tuner
Data input from the tuner
System reset input
Serial control latch signal output to the tuner
Not used (open)
Not used (connected to ground)
Ground
Clock output (16MHz)
Clock input (16MHz)
Power supply (+3.3V (STBY))
Resets IC405, 408, 411
IC405, 408, 411 NS mute
Not used (pull down)
Not used (pull down)
Latches IC411
Latches IC408
Latches IC405
Controls IC404, 406, 407, 410, 412
Reset signal output to LC89056W
Selects IC111 output clock
Clock signal output to LC89056W
Chip enable signal output to LC89056W
Write data output to LC89056W
Read data input from LC89056W
PLL lock error, data error flag input from LC89056W
Source clock selection monitor input from LC89056W
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