Sony STR-KSL900W Service Manual ▷ View online
33
STR-KSL900W
Pin No.
Pin Name
I/O
Description
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at “H” in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
TST1
O
Not used
56
BST
I
Boot strap signal input from the system controller Not used
57
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
Fixed at “H” in this set
58
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
Fixed at “L” in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
—
Power supply terminal (+2.6V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal input terminal Not used
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+2.6V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.6V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
34
STR-KSL900W
Pin No.
Pin Name
I/O
Description
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync Fixed at “H” in this set
117
TST2
I
Not used
118
GP11
I
Not used
119
TST3
I
Not used
120
VDDI
—
Power supply terminal (+2.6V)
35
STR-KSL900W
DIGITAL BOARD IC1601 MB90478PF-G-177-BNDE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DATAO
I
Audio serial data input from the digital audio interface receiver
2
GP9
I
Read ready signal input from the audio digital signal processor
3
BST
O
Boot strap signal output to the audio digital signal processor
4
HCS
O
Chip select signal output to the audio digital signal processor
5
HACN
I
Acknowledge signal input from the audio digital signal processor
6
XRST
O
System reset signal output to the audio digital signal processor “L”: reset
7
PM
O
PLL initialize signal output to the audio digital signal processor
8
GP12
O
Write signal output to the audio digital signal processor
9
AK5380_ PDN
O
Power down signal output to the A/D converter “H”: power down
10
AK4355_ CSN
O
Chip select signal output to the D/A converter
11
VSS
—
Ground terminal
12
AK4355_ PDN
O
Power down signal output to the D/A converter “H”: power down
13
AK4355_ CDT
O
Serial data output to the D/A converter
14
AK4355_ CLK
O
Serial data transfer clock signal output to the D/A converter
15
CLK
O
Serial data transfer clock signal output to the tuner unit and electrical volume
16
DATA
O
Serial data output to the tuner unit and electrical volume
17
WOOFER RELAY
O
Relay drive signal output terminal (for sub woofer) “H”: relay on
18
HDOUT
I
Serial data input from the audio digital signal processor
19
HDIN
O
Serial data output to the audio digital signal processor
20
HCLK
O
Serial data transfer clock signal output to the audio digital signal processor
21
F.MUTE
O
Audio muting on/off control signal output terminal “H”: muting on
22
LATCH
O
Serial data latch pulse signal output to the electrical volume
23
VCC5
—
Power supply terminal (+3.3V)
24
ANA/DIG
O
Analog/digital selection signal output terminal “L”: analog, “H”: digital
25, 26
VIDEO-SW1,
VIDEO-SW2
O
Video input selection signal output to the video amplifier
27
FLASH2
O
Flash programming signal output terminal
28
FLASH1/SWDT
O
Flash programming signal output terminal
Serial data output terminal
Serial data output terminal
29
SCLK
O
Serial data transfer clock signal output terminal
30
XSCEN
O
Chip enable signal output terminal
31
XRST
O
System reset signal output terminal
32
VIDEO-MUTE
O
Video muting on/off control signal output to the video amplifier
33
SCL
O
Serial data transfer clock signal output to the EEPROM
34
SDA
I/O
Two-way data bus with the EEPROM
35
AVCC
—
Power supply terminal (+3.3V)
36
AVRH
I
Reference voltage (+3.3V) input terminal
37
AVSS
—
Ground terminal
38 to 40
A/D0 to A/D2
I
Front panel key input terminal (A/D input)
41
A/D3
I
Key input terminal Not used
42
VSS
—
Ground terminal
43
RDS SIGNAL
I
RDS signal input from the tuner unit (AEP and UK models only)
44
MODEL
I
Setting terminal for the model (A/D input)
45
VERSION
I
Setting terminal for the destination (A/D input)
46
NC
—
Not used
36
STR-KSL900W
Pin No.
Pin Name
I/O
Description
47
CRYSTAL SEL
—
Not used
48
STOP
I
AC off detection signal input terminal “L”: AC off
49
MD0
I
CPU operation mode setting signal input terminal
50
MD1
I
Setting terminal for the CPU operation mode Fixed at “H” in this set
51
MD2
I
CPU operation mode setting signal input terminal
52
RDS CLOCK
I
RDS interrupt clock signal input from the tuner unit (AEP and UK models only)
53
RDS DATA
I
RDS serial data input from the tuner unit (AEP and UK models only)
54
SIRCS
I
Sircs signal input terminal
55
HUSE DETECT
I
Fuse open detection signal input terminal “L”: fuse opened
56
POWER KEY
I
I/
1 key input terminal “L”: power on
57
CSOD
I
CSOD signal input terminal
58
NOT IN USE
—
Not used
59
VOL (B)
I
Jog dial pulse input from the rotary encoder (B phase input) (for MASTER VOLUME)
60
VOL (A)
I
Jog dial pulse input from the rotary encoder (A phase input) (for MASTER VOLUME)
61
DIN
O
Serial data output to the fluorescent indicator tube driver
62
CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube driver
63
FL_STB
O
Strobe signal output to the fluorescent indicator tube driver
64
MUTE
O
Muting control signal output to the tuner unit
65
STEREO
I
FM stereo detection signal input from the tuner unit
66
TUNED
I
Tuned detection signal input from the tuner unit
67
PROTECTOR
I
Protect detection signal input from the protect circuit
68
SLATCH
O
Serial data latch pulse signal output to the tuner unit
69
DO
I
Serial data input from the tuner unit
70
FRONT RELAY
O
Relay drive signal output (for front speaker) “H”: relay on
71
CENTER RELAY
O
Relay drive signal output terminal (for center) “H”: relay on
72
REAR RELAY
O
Relay drive signal output (for surround (rear)) “H”: relay on
73
F_CTRL1
O
Fan motor on/off control signal output terminal Not used
74
F_CTRL2
O
Fan motor speed control signal output terminal
75
FAN_CLK
I
Fan motor feedback clock signal input terminal
76
FAN_ON
I
Fan motor level detection signal input terminal
77
RSTX
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
78
POWER RELAY
O
Relay drive signal output terminal (for main power) “H”: relay on
79
X1A
O
Sub system clock output terminal Not used
80
X0A
I
Sub system clock input terminal Not used
81
VSS
—
Ground terminal
82
X0
I
Main system clock input terminal (16.5 MHz)
83
X1
O
Main system clock output terminal (16.5 MHz)
84
VCC3
—
Power supply terminal (+3.3V)
85
NOT IN USE
—
Not used
86
NC
—
Not used
87
NOT IN USE
—
Not used
88
LRCK_SW
O
Signal selection signal output terminal Not used
Click on the first or last page to see other STR-KSL900W service manuals if exist.