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Model
STR-KM7600
Pages
78
Size
6.62 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
str-km7600.pdf
Date

Sony STR-KM7600 Service Manual ▷ View online

STR-KM7600
53
•  IC Pin Function Description
DIGITAL BOARD (3/4)  IC2006  ADSP21266SKSTZ-2C (DSP)
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V)
2, 3
CLKCFG0,
CLKCFG1
I
Clock frequency setting terminal
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode setting terminal for DSP
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V)
14
GND
-
Ground terminal
15
FRAG0
O
Interrupt status output to the system controller
16
FRAG1
I
PLL lock error signal and data error fl ag input terminal
17
AD7
I/O
Two-way data bus and address signal output with S-RAM    Not used
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V)
24 to 26
AD6 to AD4
I/O
Two-way data bus and address signal output with S-RAM    Not used
27
VDDINT
-
Power supply terminal (+1.2V)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way data bus and address signal output with S-RAM    Not used
31
VDDEXT
-
Power supply terminal (+3.3V)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way data bus and address signal output with S-RAM    Not used
35
XWR
O
Data write enable signal output to the S-RAM    "L": active    Not used
36, 37
VDDINT
-
Power supply terminal (+1.2V)
38
GND
-
Ground terminal
39
XRD
O
Read strobe signal output to the S-RAM    "L": active    Not used
40
ALE
O
Address latch enable signal output terminal    Not used
41 to 43
AD15 to AD13
I/O
Two-way data bus and address signal output with S-RAM    Not used
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V)
46
AD12
I/O
Two-way data bus and address signal output with S-RAM    Not used
47
VDDINT
-
Power supply terminal (+1.2V)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way data bus and address signal output with S-RAM    Not used
53
A16
O
Address signal output to S-RAM    Not used
54
VDDINT
-
Power supply terminal (+1.2V)
55
GND
-
Ground terminal
56, 57
A17, A18
O
Address signal output to S-RAM    Not used
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V)
60
VDDINT
-
Power supply terminal (+1.2V)
61
GND
-
Ground terminal
62
PF_CE
I/O
Chip enable signal input/output terminal    Not used
63
SPI_MAS
O
Master/slave selection signal output terminal    "L": DSP is master    Not used
64
DPSOA
O
PCM audio signal (front L/R) output to the D/A converter
65
DPSOB
O
PCM audio signal (surround L/R) output to the D/A converter
66
VDDINT
-
Power supply terminal (+1.2V)
STR-KM7600
54
Pin No.
Pin Name
I/O
Description
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V)
69
GND
-
Ground terminal
70
DPSOC
O
PCM audio signal (center, sub woofer) output to the D/A converter
71
DPSOD
O
PCM audio signal (surround back L/R) output to the D/A converter
72
VDDINT
-
Power supply terminal (+1.2V)
73
VDDEXT
-
Power supply terminal (+3.3V)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V)
76
GND
-
Ground terminal
77
DPSOE
O
PCM audio signal output terminal    Not used
78
DPSIA
I
PCM audio signal (digital input) input from the digital audio interface receiver
79
DPSIB
I
PCM audio signal (front L/R) input terminal
80
DPSIC
I
PCM audio signal (surround L/R) input terminal
81
DPSID
I
PCM audio signal (center, sub woofer) input terminal
82
DPSIE
I
PCM audio signal (surround back L/R) input terminal
83
VDDINT
-
Power supply terminal (+1.2V)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the D/A converter for PCM audio output
87
DPDVBCK
O
Bit clock signal output to the D/A converter for PCM audio output
88
DPLRCK
I
L/R sampling clock signal input terminal for PCM audio input
89
DPBCK
I
Bit clock signal input terminal for PCM audio input
90
VDDINT
-
Power supply terminal (+1.2V)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V)
94
DPFSCK
I
Master clock signal input terminal
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V)
97
XNONAUDIO
I
Digital input signal switch control signal input from the digital audio interface receiver
98
XSF_CE
O
Chip enable signal output terminal    Not used
99
VDDINT
-
Power supply terminal (+1.2V)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V)
121
XRESET
I
System reset signal input from the system controller
122
XSPIDS
I
Serial data latch pulse signal input from the system controller
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V)
125
SPICLK
I/O
Serial data transfer clock signal input/output with the system controller
STR-KM7600
55
Pin No.
Pin Name
I/O
Description
126
MISO
O
Serial data output to the main system controller
127
MOSI
I
Serial data input from the main system controller
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V)
130
VDDEXT
-
Power supply terminal (+3.3V)
131
AVDD
-
Power supply terminal (+3.3V)
132
AVSS
-
Ground terminal
133
GND
-
Ground terminal
134
CLKOUT
-
Not used
135
XEMU
-
Not used
136
TDO
-
Not used
137
TDI
-
Not used
138
CTRST
-
Not used
139
TCK
-
Not used
140
TMS
-
Not used
141
GND
-
Ground terminal
142
CLKIN
I
System clock input terminal (25 MHz)
143
XTAL
O
System clock output terminal (25 MHz)
144
VDDEXT
-
Power supply terminal (+3.3V)
STR-KM7600
56
DIGITAL BOARD (1/4)  IC2007 MB91353APMT-G-124E1 (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Description
1
COM_CLK
O
Data clock signal output for DIR IC and 8 CH DAC IC
2
COM_DATA
O
Data output for DIR IC and 8 CH DAC IC
3
FL_RESET
O
Reset signal output for FL DISPLAY DRIVER IC
4
HP_RY
O
Headphone relay driver control signal output
5
HP_DETECT
I
Headphone detection signal input
6
BRIDGEABLE_RY
O
Bridgeable relay control signal output
7
FL_LAT
O
Latch signal output for FL DISPLAY DRIVER IC
8
FL_CLK
O
Clock signal output for FL DISPLAY DRIVER IC
9
FL_DATA
O
Serial data output for FL DISPLAY DRIVER IC
10
TUNING A
Not Used
11
TUNING B
Not Used
12
TUNE_LAT
O
Serial latch signal output for tuner pack
13
TUNE_DI
O
Serial data output for tuner pack
14
T_CLK
O
Clock signal output for tuner pack
15
TUNE_DO
I
Tuner IF data input from tuner pack
16
HDMI_REG_CTRL
O
HDMI regulator control signal output
17
DSP_SEL
O
DSP select signal output
18
VSS
Ground
19
VCC
Power supply pin (+3.3 V)
20
RDS DATA
I
RDS data input (AEP, UK model)
21 to 24
V_SW4 to V_SW1
O
Video select signal output for COMPONENT VIDEO SELECT IC
25, 26
COMP_S1, COMP_S2
O
Component video select signal output for COMPONENT VIDEO SELECT IC
27
PS(V-MUTE)
O
Video mute signal output for COMPONENT VIDEO SELECT IC
28
CEC_OUT
O
CEC signal output
29
FUSE_DETECT
I
Fuse open detection signal input
30
HDMI_ERR
I
Error detection signal input from HDMI CONTROL IC
31
DAC_LAT
O
Latch signal output for DAC
32
DAC_MUTE
O
Mute signal output for 8CH DAC IC
33
RDS_SIGNAL
I
TUNER SD signal detection input
34
VOL_DA
O
Serial data output for DIR IC
35
VOL_CL
O
Clock signal output for DIR IC
36
PROTECTOR
I
Protector detection signal input
37
SUB_TRANS
O
Sub transformer voltage detection signal output
38
DIR_XMODE(RESET)
O
System reset (Xmode) signal output for DIR IC
39
DIRCKST
O
Clock select signal output for DIR IC
40
VSS
Ground
41
I2C_SCL
Not Used
42
I2C_SDA
Not Used
43
VSS
Ground
44
VCC
Power supply pin (+3.3 V)
45
SRC_MUTE
Not Used
46
POWER_RY
O
Power relay control signal output
47
DIR_CE(LAT)
O
Latch signal output for DIR IC
48
DIR_DO
I
Data input from DIR IC
49
DIR_ERROR
I
Error detection signal input from DIR IC
50
HDMI_FSRATE
I
FSRATE signal input
51
NMI
Not used (Fixed at H)
52
MD2
Selection of micon operation mode (Fixed at H)
53, 54
MD1, MD0
Selection of micon operation mode (Connect to VSS)
55
INIT
External reset signal input
56
VCC
Power supply pin (+3.3 V)
57
X1
Clock signal output (12.5 MHz)
58
X0
Clock signal input (12.5 MHz)
59
VSS
Ground
60
X0A
Not used (Connect to VSS)
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