Sony STR-KM3500 Service Manual ▷ View online
STR-KM3500
33
59
MULTI_ST
-
Not used
60
NIGHT_MODE
-
Not used
61
PROTECTOR
I
Protector detection signal input
62
HP_RY
O
Headphone relay driver control signal output
63
FUSE_DETECT
I
Fuse open detection signal input
64
VOL_ENCODER (B)
I
MASTER VOLUME encoder (B) signal input
65
VOL_ENCODER (A)
I
MASTER VOLUME encoder (A) signal input
66
C/REAR
O
Center / surround speaker relay driver control signal output
67
SB_RY/SW
O
SubWoofer speaker relay driver control signal output
68
Bridgeable RY
O
Bridgeable relay control signal output
69
PREOUT SW Relay
O
SubWoofer speaker relay driver control signal output
70
FRONT A(activeSW)
O
Front speaker relay driver control signal output
71
NO_USED
-
Not used
72
NO_USED
-
Not used
73
FL_RESET
O
Reset signal o/p for FL Display Driver IC
74
FL_CLK
O
Clock signal output for FL DISPLAY DRIVER IC
75
FL_DATA
O
Serial data output for FL DISPLAY DRIVER IC
76
FL_LAT
O
Latch signal output for FL DISPLAY DRIVER IC
77
RSTX
I
Reset signal input
78
TUNER_SD
I
Tuner detection signal input
79
X1A
-
Not used (Open)
80
X0A
-
Not used (connect to VSS)
81
Vss
-
Ground
82
X0
I
Clock signal input (24 MHz)
83
X1
I
Clock signal input (24 MHz)
84
Vcc3
-
Power Supply pin (+3.3v)
85
+5.8V_CTRL(HDMI)
/ NC
-
not used
86
RESET_HDMI / OED
-
not used
87
+5V_CTRL(HDMI) /
CTRL
-
not used
88
HDMI_DET
-
not used
89
D0/SD/ST
I
Tuner serial data input
90
TUNER_CLK
O
Serial clock signal output for tuner pack
91
TUNER_DATA
O
Serial data output for tuner pack
92
SLATCH
O
Tuner latch signal output
93
DIR_XMODE
O
Xmode signal output for DIR IC
94
DIR_CKSEL1
O
Clock select signal output for DIR IC
95
DIR_CLK
O
Data clock signal output for DIR IC
96
DIR_CE
O
Latch signal output for DIR IC
97
DIR_DI
O
Data output for DIR IC
98
DIR_DO
I
Data input from DIR IC
99
DIR_ERROR
I
Error detection signal input from DIR IC
100
NO_USED
-
Not used
STR-KM3500
34
DIGITAL BOARD IC1501 ADSST-AVR-1115
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V)
2, 3
CLKCFG0,
CLKCFG1
I
Clock frequency setting terminal
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode setting terminal for DSP
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V)
14
GND
-
Ground terminal
15
FRAG0
O
Interrupt status output to the system controller
16
FRAG1
I
PLL lock error signal and data error fl ag input terminal
17
AD7
I/O
Two-way data bus and address signal output with S-RAM Not used
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V)
24 to 26
AD6 to AD4
I/O
Two-way data bus and address signal output with S-RAM Not used
27
VDDINT
-
Power supply terminal (+1.2V)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way data bus and address signal output with S-RAM Not used
31
VDDEXT
-
Power supply terminal (+3.3V)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way data bus and address signal output with S-RAM Not used
35
XWR
O
Data write enable signal output to the S-RAM "L": active Not used
36, 37
VDDINT
-
Power supply terminal (+1.2V)
38
GND
-
Ground terminal
39
XRD
O
Read strobe signal output to the S-RAM "L": active Not used
40
ALE
O
Address latch enable signal output terminal Not used
41 to 43
AD15 to AD13
I/O
Two-way data bus and address signal output with S-RAM Not used
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V)
46
AD12
I/O
Two-way data bus and address signal output with S-RAM Not used
47
VDDINT
-
Power supply terminal (+1.2V)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way data bus and address signal output with S-RAM Not used
53
A16
O
Address signal output to S-RAM Not used
54
VDDINT
-
Power supply terminal (+1.2V)
55
GND
-
Ground terminal
56, 57
A17, A18
O
Address signal output to S-RAM Not used
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V)
60
VDDINT
-
Power supply terminal (+1.2V)
61
GND
-
Ground terminal
62
PF_CE
I/O
Chip enable signal input/output terminal Not used
63
SPI_MAS
O
Master/slave selection signal output terminal "L": DSP is master Not used
64
DPSOA
O
PCM audio signal (front L/R) output to the D/A converter
65
DPSOB
O
PCM audio signal (surround L/R) output to the D/A converter
66
VDDINT
-
Power supply terminal (+1.2V)
STR-KM3500
35
Pin No.
Pin Name
I/O
Description
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V)
69
GND
-
Ground terminal
70
DPSOC
O
PCM audio signal (center, sub woofer) output to the D/A converter
71
DPSOD
O
PCM audio signal (surround back L/R) output terminal Not used
72
VDDINT
-
Power supply terminal (+1.2V)
73
VDDEXT
-
Power supply terminal (+3.3V)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V)
76
GND
-
Ground terminal
77
DPSOE
O
PCM audio signal output terminal Not used
78
DPSIA
I
PCM audio signal (digital input) input from the digital audio interface receiver
79
DPSIB
I
PCM audio signal (front L/R) input from the A/D converter
80
DPSIC
I
PCM audio signal (surround L/R) input terminal Not used
81
DPSID
I
PCM audio signal (center, sub woofer) input terminal Not used
82
DPSIE
I
PCM audio signal (surround back L/R) input terminal Not used
83
VDDINT
-
Power supply terminal (+1.2V)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the D/A converter for PCM audio output
87
DPDVBCK
O
Bit clock signal output to the D/A converter for PCM audio output
88
DPLRCK
I
L/R sampling clock signal input terminal for PCM audio input
89
DPBCK
I
Bit clock signal input terminal for PCM audio input
90
VDDINT
-
Power supply terminal (+1.2V)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V)
94
DPFSCK
I
Master clock signal input terminal
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V)
97
XNONAUDIO
I
Digital input signal switch control signal input from the digital audio interface receiver
98
XSF_CE
O
Chip enable signal output terminal Not used
99
VDDINT
-
Power supply terminal (+1.2V)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V)
121
XRESET
I
System reset signal input from the system controller
122
XSPIDS
I
Serial data latch pulse signal input from the system controller
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V)
125
SPICLK
I/O
Serial data transfer clock signal input/output with the system controller
STR-KM3500
36
Pin No.
Pin Name
I/O
Description
126
MISO
O
Serial data output to the main system controller
127
MOSI
I
Serial data input from the main system controller
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V)
130
VDDEXT
-
Power supply terminal (+3.3V)
131
AVDD
-
Power supply terminal (+3.3V)
132
AVSS
-
Ground terminal
133
GND
-
Ground terminal
134
CLKOUT
-
Not used
135
XEMU
-
Not used
136
TDO
-
Not used
137
TDI
-
Not used
138
CTRST
-
Not used
139
TCK
-
Not used
140
TMS
-
Not used
141
GND
-
Ground terminal
142
CLKIN
I
System clock input terminal (25 MHz)
143
XTAL
O
System clock output terminal (25 MHz)
144
VDDEXT
-
Power supply terminal (+3.3V)
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