DOWNLOAD Sony STR-DN840 Service Manual ↓ Size: 6.81 MB | Pages: 100 in PDF or view online for FREE

Model
STR-DN840
Pages
100
Size
6.81 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
str-dn840.pdf
Date
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STR-DN840
61
Pin No.
Pin Name
I/O
Description
1
VCC
-
Power supply pin (+3.3V)
2
EVOL_CLK
O
Serial data transfer clock signal output to the electrical volume
3
EVOL_DATA
O
Serial data output to electrical volume
4
HP_DET
I
Headphone detection signal input
5
MHL_MD0
(EXT INT 15)
I
MHL signal detect
6
V_SEL_SW2
O
Composite video output signal switch
7
V_SEL_SW1
O
Composite video output signal switch
8
V_MUTE
O
Video muting control signal output to the video amplifi er
9
FL_ENABLE
I
Enable control for FL DISPLAY DRIVER IC
10
TUNER_CLK
O
Serial data transfer clock signal output to the tuner (FM/AM)
11
TUNER_MOSI
I/O
Serial data output to the tuner (FM/AM)
12
TUN_RDS_SIGNAL
I
RDS data signal input (for destination that support RDS only)
13
TUNER_CE
O
Serial data latch pulse signal output to the tuner (FM/AM)
14
DIR FSRATE
I
Sampling rate frequency from the digital audio interface receiver
15
DAC_IIC_SDL
I
IIC clock signal input from the D/A converter
16
DAC_IIC_SCA
I/O
IIC data input from the D/A converter
17
DIR_INT
I
DIR interrupt
18
DIR_XSTATE
I
Clock selection signal input from the digital audio interface receiver
19
DIR_SIGNAL
I
Audio serial data input from the digital audio interface receiver
20
DIR_RST
O
Reset signal output to the digital audio interface receiver
21
DIR_CE
O
Chip enable signal output to the digital audio interface receiver
22
DIR_MISO
I
Serial data input from digital audio interface receiver
23
DIR _SPICLK
O
Serial clock output to digital audio interface receiver
24
DIR_MOSI
O
Serial data output to digital audio interface receiver
25
VSS
-
Ground terminal
26
VCC
-
Power supply pin (+3.3V)
27
DSP_INT
I
Interrupt status signal input from DSP
28
DSP_SFLASH_HOLD
O
Hold signal output to the serial fl ash
29
DSP_RST
O
System reset signal output to the DSP “L” reset
30
NW_ADC_RST
O
Network: Disable (mute) the ADC
31
DSP_NPCM
I
SPDIF / IIS NPCM signal input from digital audio interface receiver / HDMI receiver
32
DSP_ERROR
I
SPDIF / IIS Error signal input from digital audio interface receiver / HDMI receiver
33
C
-
Regulator stabilization capacity connecting pin
34
VSS
-
Ground terminal
35
VCC
-
Power supply pin (+3.3V)
36
HDMI_CECOUT
O
CEC serial data output to the HDMI connector
37
DSP_SPICS
O
Chip select signal output to DSP
38
INITX
-
Main Micom Reset port
39
DSP_MISO
I
Serial data input from the serial fl ash and DSP
40
DSP_MOSI
O
Serial data output to the serial fl ash and DSP
41
DSP_SPICLK
O
Serial data transfer clock signal output to the serial fl ash and DSP
42
VCOM_RESET
O
Video Micom Ext Reset Input Pin
43
No_Use
-
Not used
44
VCOM_SDA (OUT)
O
IIC data output to the video micom
45
MU UART IN
I
IIC data input from the video micom
46
MD1
-
Selection of micon operation mode (Connect to VSS)
47
MD0
-
Selection of micon operation mode (Connect to VSS)
48
PE2/X0
-
Main oscillator connecting pin
49
PE3/X1
-
Main oscillator connecting pin
50
VSS
-
Ground terminal
51
VCC
-
Power supply pin (+3.3V)
52
INPUT_JOG
I
Function encoder signal input
53
FL_LAT
O
Latch signal output for FL DISPLAY DRIVER IC
•  IC Pin Function Descriptions
DIGITAL BOARD (4/8)  IC2100  MB9AF156NPMC-G-JNK1E2 (SYSTEM CONTROL)
Ver. 1.3
STR-DN840
62
Pin No.
Pin Name
I/O
Description
54
FL_DATA
O
Serial data output for FL DISPLAY DRIVER IC
55
FL_CLK
O
Clock signal output for FL DISPLAY DRIVER IC
56
HDMI_CECIN
I
CEC serial data input from the HDMI connector
57
AD_KEY1
I
Key signal input (A/D port)
58
AD_KEY2
I
Key signal input (A/D port)
59
SIRCS_IN
I
SIRCS signal input
60
AVCC
-
Analog power supply pin for A/D converter
61
AVRH
-
Standard power supply pin for A/D converter
62
AVSS
-
Analog ground for A/D converter
63
VOLUME_JOG
I
MASTER VOLUME encoder signal input
64
White_LED
I
White LED control port
65
POWER_KEY
I
Power switch input terminal
66
LIMITER 
I
Limiter signal input
67
TEMP_SENSOR_2
I
Thermal detection signal input from the thermal sensor
68
TEMP_SENSOR_1
I
Thermal detection signal input from the thermal sensor
69
DCAC_MUTE
O
DCAC MIC Mute
70
FL_BK
O
Blanking period signal output to the fl uorescent indicator tube
71
FLASH_CLK/PWER_
LED
O
Power on/standby LED control port
72
SO
O
Serial data output terminal (use for Firmware Flash Program)
73
SI
I
Serial data input terminal (use for Firmware Flash Program)
74
BT_MUTE
I
Bluetooth: Mute request from BT device to Video uCOM
75
VSS
-
Ground terminal
76
VCC
-
Power supply pin (+3.3V)
77
WF_HDMI_SEL
O
Audio selection between NETWORK and HDMI block
78
TCK
-
Test clock signal input terminal (for JTAG) Not used
79
TDI
-
Test data input terminal (for JTAG) Not used
80
TMS
-
Test mode selection signal input terminal (for JTAG) Not used
81
TDO
-
Test data output terminal (for JTAG) Not used
82
STDBY_LED
O
Standby LED
83
NW_WAKE
I
Network wake up pin
84
PWR_SW_B
O
Power control port B
85
PWR_SW_A
O
Power control port A
86
HP_RY
O
Relay drive signal (for headphone) output terminal “H”: relay on
87
BRIDGEABLE_RY
O
Relay drive signal (for power supply) output terminal “H”: relay on
88
SBL_SBR_RY
O
Relay drive signal (for surround back) output terminal “H”: relay on
89
ZONE2_PREOUT_
SW_RY
O
Relay drive signal (for sub woofer) output terminal “H”: relay on
90
FRONT_SPK_RY
O
Relay drive signal (for front) output terminal “H”: relay on
91
C/SL_SR_RY
O
Relay drive signal (for center and surround) output terminal “H”: relay on
92
PROTECT
I
Protect detection signal input terminal
93
AC_CUT
I
AC off detection signal input
94
E2P_SCL
O
Serial data transfer clock signal output to the EEPROM
95
E2P_SDA
I/O
Two-way data bus with the EEPROM
96
V_COMP_SW2
O
Component video selection signal output to the video amplifi er
97
VCC
-
Power supply pin (+3.3V)
98
POWER_RY
O
Relay drive signal (for main power) output terminal “H”: relay on
99
FUSE_DET
I
Fuse open detect signal input
100
VSS
-
Ground terminal
Ver. 1.1
STR-DN840
63
DIGITAL BOARD (5/8)  IC2502 ADSST-AVR-3046 (DSP)
Pin No.
Pin Name
I/O
Description
1
SDDQM
O
Data mask signal output to the SD-RAM
2
MS0
O
Memory select signal output to the SD-RAM
3
SDCKE
O
Clock enable signal output to the SD-RAM
4
VDD_INT
-
Power supply terminal (+1.2V) (for core)
5
CLK_CFG1
I
Clock frequency setting terminal     Fixed at “L” in this unit
6
ADDR0
O
Address signal output to the SD-RAM
7
BOOT_CFG0
I
Boot mode selection signal input terminal     Fixed at “H” in this unit
8
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
9 to 13
ADDR1 to ADDR5
O
Address signal output to the SD-RAM
14
BOOT_CFG1
I
Serial data input from the main system controller
15
GND
-
Ground terminal
16, 17
ADDR6, ADDR7
O
Address signal output to the SD-RAM
18, 19
NC
-
Not used
20, 21
ADDR8, ADDR9
O
Address signal output to the SD-RAM
22
CLK_CFG0
I
Clock frequency setting terminal     Fixed at “L” in this unit
23
VDD_INT
-
Power supply terminal (+1.2V) (for core)
24
CLKIN
I
System clock input terminal (25 MHz)
25
XTAL2
O
System clock output terminal     Not used
26
ADDR10
O
Address signal output terminal     Not used
27
SDA10
O
Address signal output to the SD-RAM
28
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
29
VDD_INT
-
Power supply terminal (+1.2V) (for core)
30
ADDR11
O
Address signal output to the SD-RAM
31
ADDR12
O
Address signal output terminal     Not used
32
ADDR17
O
Bank address signal output to the SD-RAM
33
ADDR13
O
Address signal output terminal     Not used
34
VDD_INT
-
Power supply terminal (+1.2V) (for core)
35
ADDR18
O
Bank address signal output to the SD-RAM
36
RESETOUT/
RUNRSTIN
I/O
Reset signal output terminal/Running reset signal input terminal     Not used
37
VDD_INT
-
Power supply terminal (+1.2V) (for core)
38
MOSI
I
Serial data input from the main system controller
39
MISO
O
Serial data output to the main system controller
40
SPICLK
I
Serial data transfer clock signal input from the main system controller
41
VDD_INT
-
Power supply terminal (+1.2V) (for core)
42
DPI_P05
I
Chip select signal input from the main system controller
43
DSP_CS
I
Chip select signal input from the main system controller
44
MD
-
Not used
45
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
46
NC
-
Not used
47
RESET_MAIN
I
Reset signal input terminal     Not used
48
VDD_INT
-
Power supply terminal (+1.2V) (for core)
49
UART_OUT
O
Serial data output terminal     Not used
50
UART_IN
I
Serial data input terminal     Not used
51
LED
O
Not used
52 to 56
NC
-
Not used
57
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
58 to 61
NC
-
Not used
62
VDD_INT
-
Power supply terminal (+1.2V) (for core)
63, 64
NC
-
Not used
65
VDD_INT
-
Power supply terminal (+1.2V) (for core)
66, 67
NC
-
Not used
68
VDD_INT
-
Power supply terminal (+1.2V) (for core)
69
NC
-
Not used
STR-DN840
64
Pin No.
Pin Name
I/O
Description
70
WDTRSTO
O
Watchdog timer reset output terminal     Not used
71
NC
-
Not used
72
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
73
SL/SR_OUT
O
Audio signal output to the DSP2
74
SL/SR_IN
I
Audio signal input terminal
75
BCLK_IN
I
Bit clock signal input terminal
76
OPTION_L/
OPTION_R_OUT
O
Audio signal output to the DSP2
77
FRONTHI_L/R_OUT
O
Audio signal output to the DSP2
78
VDD_INT
-
Power supply terminal (+1.2V) (for core)
79 to 83
NC
-
Not used
84
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
85
VDD_INT
-
Power supply terminal (+1.2V) (for core)
86
L/R_OUT
O
Audio signal output to the DSP2
87
MID/SW2_OUT
O
Audio signal output terminal     Not used
88
SBL/SBR_OUT
O
Audio signal output to the DSP2
89
ZONE_L/R
O
Not used
90
VDD_INT
-
Power supply terminal (+1.2V) (for core)
91
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
92
MCLK_IN
I
Master clock signal input from the frequency multiplier
93
VDD_INT
-
Power supply terminal (+1.2V) (for core)
94
C/SW1_OUT
O
Audio signal output to the DSP2
95
C/SW_IN
I
Audio signal input terminal
96
A/D_2CH
I
Audio signal input terminal
97
LRCLK_IN
I
L/R sampling clock signal input terminal
98
BCLK_OUT
O
Bit clock signal output to the DSP2
99
LRCLK_OUT
O
L/R sampling clock signal output to the DSP2
100
L/R_IN
I
Audio signal input terminal
101
SBL/SBR_IN
I
Audio signal input terminal
102
VDD_INT
-
Power supply terminal (+1.2V) (for core)
103
DIR_IN
I
Audio signal input terminal
104
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
105
VDD_INT
-
Power supply terminal (+1.2V) (for core)
106
BOOT_CFG2
I
Boot mode selection signal input terminal      Fixed at “L” in this unit
107
VDD_INT
-
Power supply terminal (+1.2V) (for core)
108
AMI_ACK
I
Memory acknowledge terminal     Not used
109
GND
-
Ground terminal
110
THD_M
O
Thermal diode cathode output terminal     Not used
111
THD_P
I
Thermal diode anode input terminal     Not used
112
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
113, 114
VDD_INT
-
Power supply terminal (+1.2V) (for core)
115
MS1
O
Memory select terminal     Not used
116
VDD_INT
-
Power supply terminal (+1.2V) (for core)
117
WDT_CLKO
O
Watchdog resonator pad output terminal     Not used
118
WDT_CLKIN
I
Watchdog timer clock input terminal     Fixed at “L” in this unit
119
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
120 to
122
ADDR23 to ADDR21
O
Address signal output terminal Not used
123
VDD_INT
-
Power supply terminal (+1.2V) (for core)
124, 125
ADDR20, ADDR19
O
Address signal output terminal     Not used
126
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
127, 128
ADDR16, ADDR15
O
Address signal output terminal     Not used
129
VDD_INT
-
Power supply terminal (+1.2V) (for core)
130
ADDR14
O
Address signal output terminal     Not used
131
AMI_WR
O
AMI port write enable terminal     Not used
132
AMI_RD
O
AMI port read enable terminal     Not used
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