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1

VDD_INT

-

Power supply terminal (+1.2V) (for core)

2

CLK_CFG1

I

Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the 
operating frequency can be changed by programming the PLL multiplier and divider in the 
PMCTL register at any time after the core comes out of reset. The allowed values are: 
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved

3

BOOT_CFG0

I

Boot Confi guration Select. These pins select the boot mode for the processor.

4

VDD_EXT

-

Power supply terminal (+3.3V) (for I/O)

5

VDD_INT

-

Power supply terminal (+1.2V) (for core)

6

BOOT_CFG1

I

Boot Confi guration Select. These pins select the boot mode for the processor.

7

GND

-

Ground terminal

8

NC

-

Not used

9

NC

-

Not used

10

CLK_CFG0

I

Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the 
operating frequency can be changed by programming the PLL multiplier and divider in the 
PMCTL register at any time after the core comes out of reset. The allowed values are: 
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved

11

VDD_INT

-

Power supply terminal (+1.2V) (for core)

12

CLKIN

I

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It confi gures the 
processors to use either its internal clock generator or an external clock source.

13

XTAL

O

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

14

VDD_EXT

-

Power supply terminal (+3.3V) (for I/O)

15, 16

VDD_INT

-

Power supply terminal (+1.2V) (for core)

17

RESETOUT/RUNRSTIN

I/O

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also has a 
second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL register. 
For more information, see the ADSP-214xx SHARC Processor Hardware Reference.

18

VDD_INT

-

Power supply terminal (+1.2V) (for core)

19

MOSI

I

Serial data input from the main system controller

20

MISO

O

Serial data output to the main system controller

21

SPICLK

I

Serial data transfer clock signal input from the main system controller

22

VDD_INT

-

Power supply terminal (+1.2V) (for core)

23

DPI_P05

I/O

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The 
DPI SRU confi guration registers defi ne the combination of on-chip peripheral inputs or 
outputs connected to the pin and to the pin’s output enable. The confi guration registers of 
these peripherals then determines the exact behavior of the pin. Any input or output signal 
present in the DPI SRU may be routed to any of these pins.

24

DSP_CS

I

Chip select signal input from the main system controller

25

MD

-

Not used

26

VDD_EXT

-

Power supply terminal (+3.3V) (for I/O)

27

DPI_P08

-

Not used

28

RESET_MAIN

I

Reset signal input terminal

29

VDD_INT

-

Power supply terminal (+1.2V) (for core)

30

UART_OUT

O

Serial data output terminal

31

UART_IN

I

Serial data input terminal

32

LED

O

Not used

33, 34

DPI_P12, DPI_P13

-

Not used

35

DAI_P03

-

Not used

36

DPI_P14

-

Not used

37 to 39

VDD_INT

-

Power supply terminal (+1.2V) (for core)

40

SL/SR_IN

I

Audio signal input terminal for SL/SR

41

SL/SR_OUT

O

Audio signal output to the DSP2 for SL/SR

42

BCLK_IN

I

Bit clock signal input terminal

43

OPTION_L/

OPTION_R_OUT

-

Not used

44

FRONTHI_L/R_OUT

-

Not used

45

VDD_INT

-

Power supply terminal (+1.2V) (for core)

46

VDD_EXT

-

Power supply terminal (+3.3V) (for I/O)

47

VDD_INT

-

Power supply terminal (+1.2V) (for core)

48

L/R_OUT

O

Audio signal output to the DSP2 for L/R

49

MID/SW2_OUT

O

Audio signal output terminal

50

SBL/SBR_OUT

O

Audio signal output to the DSP2 for SBL/SBR

51

ZONE_L/R

-

Not used

52

VDD_INT

-

Power supply terminal (+1.2V) (for core)

53

VDD_EXT

-

Power supply terminal (+3.3V) (for I/O)

54

MCLK_IN

I

Master clock signal input from the frequency multiplier

55

VDD_INT

-

Power supply terminal (+1.2V) (for core)

56

C/SW1_OUT

O

Audio signal output to the DSP2 for C/SW

57

A/D_2CH

I

Audio signal input terminal for L/R

58

C/SW_IN

I

Audio signal input terminal for C/SW

59

LRCLK_IN

I

L/R sampling clock signal input terminal

60

BCLK_OUT

O

Bit clock signal output to the DSP2

61

LRCLK_OUT

O

L/R sampling clock signal output to the DSP2

62

SBL/SBR_IN

I

Audio signal input terminal for SBL/SBR

63

L/R_IN

I

Audio signal input terminal for Analog L/R from DIR IC

64

VDD_INT

-

Power supply terminal (+1.2V) (for core)

65

DIR_IN

I

Audio signal input terminal

66, 67

VDD_INT

-

Power supply terminal (+1.2V) (for core)

68

GND

-

Ground terminal

69

THD_M

-

Not used

70

THD_P

-

Not used

71

VDD_THD

-

Thermal diode power supply

72 to 76

VDD_INT

-

Power supply terminal (+1.2V) (for core)

77

FLAG0

I/O

DSP Interrupt

78, 79

VDD_INT

-

Power supply terminal (+1.2V) (for core)

80

FLAG1

I/O

DSP Error

81

FLAG2

I/O

DSP Non Audio

82

FLAG3

-

Not used

83

MLBCLK

-

Not used

84

MLBDAT

-

Not used

85

MLBDO

O

Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode. This 
serves as the output data pin in 5-pin mode. When the MLB controller is not used, this pin 
should be connected to ground.

86

VDD_EXT

-

Power supply terminal (+3.3V) (for I/O)

87

MLBSIG

I/O

Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address 
generated by the MLB Controller, as well as the Command and RxStatus bytes from MLB 
devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, this pin 
should be grounded.

88

VDD_INT

-

Power supply terminal (+1.2V) (for core)

89

MLBSO

O

Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB mode. 
This serves as the output signal pin in 5-pin mode. When the MLB controller is not used, this 
pin should be connected to ground.

90

TRST

I

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after 
power-up or held low for proper operation of the processor.

91

EMU

O

Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools product 
line of JTAG emulators target board connector only.

92

TDO

O

Test Data Output (JTAG). Serial scan output of the boundary scan path.

93

VDD_EXT

-

Power supply terminal (+3.3V) (for I/O)

94

VDD_INT

-

Power supply terminal (+1.2V) (for core)

95

TDI

I

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

96

TCK

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed 
low) after power-up or held low for proper operation of the device. 

97

VDD_INT

-

Power supply terminal (+1.2V) (for core)

98

RESET

I

Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 
CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution 
from the hardware reset vector address. The RESET input must be asserted (low) at power-
up.

99

TMS

I

Test Mode Select (JTAG). Used to control the test state machine.

100

VDD_INT

-

Power supply terminal (+1.2V) (for core)

1

VCC

O

Power supply pin (+3.3V)

2 to 4

No_Use

-

Not used

5

UPDATE_VURX

O

Update to MAIN Micom data input

6

UPDATE_VUTX

O

Update to MAIN Micom data output

7 to 9

No_Use

-

Not used

10

TEST_SCK

O

Not used

11

TEST_SDA

O

Not used

12

UPDATE_LED

O

USB Update: USB Update LED Control / NW Update LED Control

13

NON_LPCM

O

HDMI: Non LPCM Stream Info Line Notifi cation

14

MU_RST

O

USB Update: USB Update Main Micom Reset

15

MU_MD0

O

USB Update: USB Update MD0 select

16, 17

No_Use

-

Not used

18

Test_1

O

Test Pad 1 (for designer evaluation only)

19

Test_2

O

Test Pad 2 (for designer evaluation only)

20

Test_3

O

Test Pad 3 (for designer evaluation only)

21

Test_4

O

Test Pad 4 (for designer evaluation only)

22

Test_5

O

Test Pad 5 (for designer evaluation only)

23

Test_6

O

Test Pad 6 (for designer evaluation only)

24

Test_7

O

Test Pad 7 (for designer evaluation only)

25

VSS

-

Ground terminal

26

VCC

-

Power supply pin (+3.3V)

27

No_Use

-

Not used

28

Sparta_INT

I

HDMI device interrupt port

29

Sparta_RST

O

HDMI device reset control port

30

No_Use

-

Not used

31

HDMI_MUTE

O

HDMI: Audio Mute Request

32

5VPWR_A

O

HDMI: 5V Power for HDMI-Tx Device

33

C

-

Regulator stabilization capacity

34

VSS

-

Ground terminal

35

VCC

-

Power supply pin (+3.3V)

36, 37

No_Use

-

Not used

38

INITX

-

Video Micom reset port

39

No_Use

-

Not used

40

HDMI_SDA

I/O

HDMI: Communication Line - I2C SDA for HDMI-Rx, HDMI-Tx, EDID device

41

HDMI_SCK

O

HDMI: Communication Line - I2C SCK

42 to 45

No_Use

-

Not used

46, 47

MD1, MD0

-

UCOM Mode setting terminal

48, 49

X0, X1

-

Clock signal output (4MHz)

50

VSS

-

Ground terminal

51

VCC

-

Power supply pin (+3.3V)

52, 53 

No_Use

-

Not used

54

USB_IP_SDA

I/O

USB: Data Communication line - I2C SDA for iPod certifi cation IC

55

USB_IP_SCL

O

USB: Data Communication line - I2C SCL for iPod certifi cation IC

56

USB_IP_Reset

O

USB: RESET for iPod certifi cation IC

57, 58

No_Use

-

Not used

59

USB_OVC

I

USB: Overcurrent Detection

60

AVCC

-

A/D converter power supply terminal / Analog power supply pin for A/D converter

61

AVRH

-

ADC analog reference voltage input / Standard power supply pin for A/D converter

62

AVSS

-

A/D converter terminal GND / Analog ground for A/D converter

63

USB SDA

I/O

USB: Communication Line I2C SDA

64

USB_SCL

O

USB: Communication Line I2C SDL

65

USB_MCHNG

I

USB: MCHNG (change of music fi le being playback) from USB Device BU94604BKV

66

USB_PCONT

I

USB: Power control for USB device

67

USB_SEARCH

I

USB: SEARCH signal communication between USB board