Sony STR-DG820 Service Manual ▷ View online
STR-DG820
61
HDMI BOARD IC3508 SII9134CTU (HDMI TRANSCEIVER)
Pin No.
Pin Name
I/O
Description
1
DE
I
Data enable signal input from the HDMI receiver
2
HSYNC
I
Horizontal sync signal input from the HDMI receiver
3
VSYNC
I
Vertical sync signal input from the HDMI receiver
4
SPDIF
I
S/PDIF signal input from the HDMI receiver
5
MCLK
I
Master clock signal input from the HDMI receiver
6 to 9
SD3 to SD0
I
PCM audio signal input from the HDMI receiver
10
WS
I
L/R sampling clock signal input from the HDMI receiver
11
SCK
I
Bit clock signal input from the HDMI receiver
12
CVCC18
-
Power supply terminal (+1.8V)
13
GND
-
Ground terminal
14
IOVCC33
-
Power supply terminal (+3.3V)
15
DCLK
I
Not used
16
DR0
I
Not used
17
DL0
I
Not used
18
DR1
I
Not used
19
DL1
I
Not used
20
DR2
I
Not used
21
DL2
I
Not used
22
DR3
I
Not used
23
DL3
I
Not used
24
INT
O
Interrupt signal output to the HDMI controller
25
RESET#
I
Reset signal input from the HDMI controller "L": reset
26
AGND
-
Ground terminal
27
EXT_SWG
-
Not used
28
PVCC1
-
Power supply terminal (+1.8V)
29
AGND
-
Ground terminal
30
TXC-
O
TMDS clock (negative) output to the HDMI OUT connector
31
TXC+
O
TMDS clock (positive) output to the HDMI OUT connector
32
AVCC18
-
Power supply terminal (+1.8V)
33
TX0-
O
TMDS data (negative) output to the HDMI OUT connector
34
TX0+
O
TMDS data (positive) output to the HDMI OUT connector
35
AGND
-
Ground terminal
36
TX1-
O
TMDS data (negative) output to the HDMI OUT connector
37
TX1+
O
TMDS data (positive) output to the HDMI OUT connector
38
AVCC18
-
Power supply terminal (+1.8V)
39
TX2-
O
TMDS data (negative) output to the HDMI OUT connector
40
TX2+
O
TMDS data (positive) output to the HDMI OUT connector
41
AGND
-
Ground terminal
42
PVCC2
-
Power supply terminal (+1.8V)
43
AGND
-
Ground terminal
44
AVCC33
-
Power supply terminal (+3.3V)
45
DCCPWR5V
I
Power supply voltage (+5V) input terminal
46
DSCL
O
I2C clock signal output to the HDMI OUT connector
47
DSDA
I/O
I2C data bus with the HDMI OUT connector
48
CSCL
I
I2C clock signal input from the HDMI controller
49
CSDA
I/O
I2C data bus with the HDMI controller, EEPROM, and HDMI receiver
50
CI2CA
-
Not used
51
HPD
I
Hot plug detection signal input from the HDMI OUT connector
52
TMODE
-
Not used
53
IOVCC33
-
Power supply terminal (+3.3V)
54
GND
-
Ground terminal
55
VPP18
-
Power supply terminal (+1.8V)
56 to 63
D35 to D28
I
Serial data input from the HDMI receiver
64
CVCC18
-
Power supply terminal (+1.8V)
65
GND
-
Ground terminal
STR-DG820
62
Pin No.
Pin Name
I/O
Description
66
IOVCC33
-
Power supply terminal (+3.3V)
67 to 75
D27 to D19
I
Serial data input from the HDMI receiver
76
CVCC18
-
Power supply terminal (+1.8V)
77 to 86
D18 to D9
I
Serial data input from the HDMI receiver
87
GND
-
Ground terminal
88
IDCK
I
Output data clock signal input from the HDMI receiver
89
IOVCC33
-
Power supply terminal (+3.3V)
90 to 98
D8 to D0
I
Serial data input from the HDMI receiver
99
CVCC18
-
Power supply terminal (+1.8V)
100
GND
-
Ground terminal
STR-DG820
63
DSP BOARD IC5021 D790E002BZDH300 (DSP)
Pin No.
Pin Name
I/O
Description
A1
VSS
-
Ground terminal
A2
DVDD
-
Power supply terminal (+3.3V) (for IO)
A3
AFSX0
O
L/R sampling clock signal output to the D/A converter
A4
ACLKX0
O
Bit clock signal output to the D/A converter
A5
ACLKR0
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
A6
AXR0[14]/AXR2[1]
I
PCM audio signal input from the HDMI receiver
A7
VSS
-
Ground terminal
A8
AXR0[11]/AXR1[2]
I
PCM audio signal input from the A/D converter
A9
AXR0[9]/AXR1[4]/
SPI1_SIMO
I/O
Not used
A10
VSS
-
Ground terminal
A11
AXR0[6]/SPI1_ENA#
I/O
Not used
A12
AXR0[4]
I/O
Not used
A13, A14
AXR0[2], AXR0[0]
O
PCM audio signal output to the D/A converter
A15
DVDD
-
Power supply terminal (+3.3V) (for IO)
A16
VSS
-
Ground terminal
B1
DVDD
-
Power supply terminal (+3.3V) (for IO)
B2
UHPI_HBE[3]#
I
Not used
B3
AHCLKR0/AHCLKR1
I/O
Not used
B4
AFSR0
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
B5 to B7
AXR0[15]/AXR2[0],
AXR0[13]/AXR1[0],
AXR0[13]/AXR1[0],
AXR0[12]/AXR1[1]
I
PCM audio signal input from the HDMI receiver
B8
AXR0[10]/AXR1[3]
I
PCM audio signal input from the digital audio interface receiver
B9
AXR0[8]/AXR1[5]/
SPI1_SOMI
I/O
Not used
B10
AXR0[7]/SPI1/_CLK
I/O
Not used
B11
AXR0[5]/SPI1_SCS#
I/O
Not used
B12, B13
AXR0[3], AXR0[1]
O
PCM audio signal output to the D/A converter
B14
SPI0_SOMI
O
Serial data output to the system controller
B15
SPI0_SIMO
I
Serial data input from the system controller
B16
DVDD
-
Power supply terminal (+3.3V) (for IO)
C1
AMUTE0
O
Not used
C2
AHCLKX0/AHCLKX2
I
Master clock signal input from the digital audio interface receiver and HDMI receiver
C3
UHPI_HD[23]
I/O
Not used
C4 to C6
UHPI_HBE[2]# to
HPI_HBE[0]
I
Not used
C7
UHPI_HDS[2]#
I/O
Not used
C8
UHPI_HCS#
I/O
Not used
C9
UHPI_HAS#
I/O
Not used
C10
UHPI_HCNTL[1]
I/O
Not used
C11
AFSX2
I
Error signal input from the digital audio interface receiver, HDMI receiver and HDMI controller
C12
AFSR2
I
PCM audio data input from the digital audio interface receiver
C13
ACLKR2
I/O
Not used
C14
AHCLKR2
I/O
Not used
C15
SPI0_SCS#
I
Chip select signal input from the system controller
C16
SPI0_CLK
I
Serial data transfer clock signal input from the system controller
D1
AHCLKX1
I/O
Not used
D2
AMUTE1
O
Not used
D3
UHPI_HD[22]
I/O
Not used
D4, D5
DVDD
-
Power supply terminal (+3.3V) (for IO)
D6
UHPI_HRDY#
I
Not used
D7
UHPI_HDS[1]#
I/O
Not used
D8
UHPI_HRW
I
Not used
D9
UHPI_HCNTL[0]
I
Not used
D10
AMUTE2/HINT#
O
Not used
STR-DG820
64
Pin No.
Pin Name
I/O
Description
D11
ACLKX2
O
Interruput signal output to the system controller
D12, D13
DVDD
-
Power supply terminal (+3.3V) (for IO)
D14
EM_WAIT
I
Not used
D15
EM_OE#
O
Not used
D16
SPI0_ENA#
I
Chip enable signal input from the system controller
E1
ACLKR1
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
E2
ACLKX1
O
Bit clock signal output to the D/A converter
E3
UHPI_HD[21]
I/O
Not used
E4
DVDD
-
Power supply terminal (+3.3V) (for IO)
E5
VSS
-
Ground terminal
E6 to E11
CVDD
-
Power supply terminal (+1.26V) (for core)
E12
VSS
-
Ground terminal
E13
DVDD
-
Power supply terminal (+3.3V) (for IO)
E14
UHPI_HD[18]
I/O
Not used
E15
EM_CS[2]#
O
Not used
E16
EM_RW
O
Not used
F1
AFSR1
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
F2
AFSX1
O
L/R sampling clock signal output to the D/A converter
F3, F4
UHPI_HD[19],
UHPI_HD[20]
I/O
Not used
F5 to F12
VSS
-
Ground terminal
F13, F14
UHPI_HD[10],
UHPI_HD[9]
I/O
Not used
F15
EM_CS[0]#
O
Chip select signal output to the SD-RAM
F16
EM_RAS#
O
Row address strobe signal output to the SD-RAM
G1
VSS
-
Ground terminal
G2
RESET#
I
Reset signal input from the system controller "L": reset
G3, G4
UHPI_HD[17],
UHPI_HD[18]
I/O
Not used
G5
CVDD
-
Power supply terminal (+1.26V) (for core)
G6 to G11
VSS
-
Ground terminal
G12
CVDD
-
Power supply terminal (+1.26V) (for core)
G13, G14
UHPI_HD[12],
UHPI_HD[11]
I/O
Not used
G15
EM_BA[0]
O
Bank address signal output to the SD-RAM
G16
VSS
-
Ground terminal
H1
UHPI_HD[16]
I/O
Not used
H2
CLKIN
I
Not used
H3
VSS
-
Ground terminal
H4
UHPI_HD[31]
I/O
Not used
H5
CVDD
-
Power supply terminal (+1.26V) (for core)
H6 to H11
VSS
-
Ground terminal
H12
CVDD
-
Power supply terminal (+1.26V) (for core)
H13, H14
UHPI_HD[14],
UHPI_HD[13]
I/O
Not used
H15
EM_A[10]
O
Address signal output to the SD-RAM
H16
EM_BA[1]
O
Bank address signal output to the SD-RAM
J1
OSCVSS
-
Ground terminal for oscillator
J2
OSCIN
I
System clock input terminal (25 MHz)
J3
OSCOUT
O
System clock output terminal (25 MHz)
J4
OSCVDD
-
Power supply terminal for oscillator
J5
CVDD
-
Power supply terminal (+1.26V) (for core)
J6 to J11
VSS
-
Ground terminal
J12
CVDD
-
Power supply terminal (+1.26V) (for core)
J13
UHPI_HD[15]
I/O
Not used
J14
DVDD
-
Power supply terminal (+3.3V) (for IO)
J15, J16
EM_A[1], EM_A[0]
O
Address signal output to the SD-RAM
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