Sony STR-DG2100 Service Manual ▷ View online
STR-DG2100
25
25
STR-DG2100
6-2. BLOCK DIAGRAM – DSP Section –
(Page 26)
(Page 26)
(Page 26)
(Page 24)
DSP1
IC5002
DPSIB
DPSIA
DPSID
DPSIC
DPSOB
DPSOA
DPSOD
DPSOC
DPSIE
DPDVBCK
DPDVLRCK
P_ERROR
SPIDS A11
FLAG0 F2
RESET B10
DPBCK
DPLRCK
D5001
FLAG1
DPFSCK
NONAUDIO
SI_B
SI_A
SI_D
SI_C
SI_E
BCK
LRCK
DIR-ERR
MCK
DIR_NONAU
DSP1_MOSI
93
DSP1_MISO
92
RDATA0
1
DSP1_SPICLK
94
DSP1_SPIDS
11
DSP1_INT
83
DSP1_RESET
12
DSP1_BOOTCFG0
13
DSP1_BOOTCFG1
DSP1_MOSI
DSP1_MISO
DSP1_SPICLK
DSP1_SPIDS
DSP1_INT
DSP1_RESET
DSP1_BOOTCFG0
DSP1_BOOTCFG1
14
DSP2_BOOTCFG0
25
DSP2_BOOTCFG1
26
SF2_DSP2_MAS
17
SF2_CPU_CE
20
DSP2_MOSI
100
DSP2_MISO
99
DSP2_SPICLK
101
DSP2_SPIDS
21
DSP2_INT
84
DSP2_RESET
DSP2_BOOTCFG0
DSP2_BOOTCFG1
9
DSP2_SIB_SEL
10
P_ERROR
SF2_DSP2_MAS
SF2_CPU_CE
DSP2_MOSI
DSP2_MISO
DSP2_SPICLK
DSP2_SPIDS
DSP2_INT
DSP2_RESET
22
DSP CONTROLLER
IC5208
BOOTCFG1 C1
XIN 58
XOUT 57
DSP1_SPIDS
DSP1_SPICLK
DSP1_MOSI
DSP1_MISO
DSP1_BOOTCFG1
DSP1_INT
DSP1_RESET
BOOTCFG0 C2
DSP1_BOOTCFG0
SPICLK B9
MOSI A9
MISO A10
X5202
12.5MHz
: AUDIO (DIGITAL)
SIGNAL PATH
DSP2
IC5202
DPSIC
DPSIB
DPSIE
DPSIA
DPSID
DPSOB
DPSOA
DPSOD
DPSOC
DPDVBCK
DPDVLRCK
SPIDS A11
FLAG0 F2
RESET B10
SF2_DSP2_CE
SPICLK
MOSI
CE#
1
SCK
6
SI
5
SO
2
FLIP-FLOP
IC5212
SF2_CPU_CE
SF2_DSP2_MAS
DSP2_MOSI
DSP2_MISO
DSP2_SPICLK
BUFFER
IC5211
SERIAL FLASH
IC5213
DSP2_SPIDS
DSP2_INT
DSP2_RESET
C1
DSP2_BOOTCFG1
BOOTCFG0
BOOTCFG1
C2
DSP2_BOOTCFG0
DPBCK
DPLRCK
FLAG1
DPFSCK
P_ERROR
DPSOE
SI3
102
SO3
103
MD_DATA
DM_DATA
89
MD_BUSY
63
MD_INT
82
DM_BUSY
64
MD2
52
DRST_TRG
36
XRESET
55
D232C_RX
D232C_TX
MD_DATA
MD_BUSY
MD_INT
DM_BUSY
MD2
DRST_TRG
DUCOM_RESET
DM_DATA
90
SDO2
SDO1
SDO4
SDO3
LRCK
BCK
18
9
17
16
AD8 – AD15
ALE
LE
N2
M2
N3
11
S-RAM
IC5007
IC5007
CE#
ADDRESS LATCH
IC5010
IC5012
ADDRESS LATCH
IC5009
AD0 – AD7
LE
11
FLASH MEMORY
IC5006
O6 13
26
CE
8
OE
37
WE#
11
WE
15
OE#
28
RESET#
I/O0 – I/O7
DQ0 – DQ7
D0 – D7
D0 – D6
O0 – O7
O0 – O4
DQ15/A-1,
A0 – A19
A0 – A19
A0 – A18
12
ALE
DAI_P1
AD0 – AD7
LE
11
S-RAM
IC5207
IC5207
OE
ADDRESS LATCH
IC5210
ADDRESS LATCH
IC5209
RD
AD8 – AD15
LE
WR
11
DSP1_A16
41
WE
17
P10
M13
M14
L14
K14
K14
P14
G14
H13
H13
F1
F14
F13
P11
P12
P13
H14
J14
N2
N3
M2
B9
A9
A9
SF2_DSP2_MAS P9
MISO A10
E14
P15
P14
M13
M14
L14
K14
G14
H13
F1
F14
F13
P11
P10
P12
P13
N14
H14
J14
E14
X5001
12.288MHz
XTAL
CLKIN
B4
A2
X5201
25MHz
XTAL
CLKIN
B4
A2
WR
RD
RD
11 3A
10 3B
10 3B
3 1B
2 1A
DATA SELECTOR
IC5013
3Y 9
1Y 4
2Y 7
SELECT 1
6 2B
5 2A
D0 – D7
A0 – A16
I/O0 – I/O7
O0 – O7
D0 – D7
O0 – O7
STR-DG2100
26
26
STR-DG2100
6-3. BLOCK DIAGRAM – DIGITAL AUDIO Section –
(Page 25)
(Page 27)
(Page 32)
(Page 33)
(Page 28)
(Page 32)
(Page 33)
(Page 32)
(Page 24)
(Page 25)
(Page 28)
(Page 24)
(Page 29)
(Page 25)
39
X0
40
X1
174
EEPROM_SDA
59
MUTE
62
56
55
AVSYNC_XCS
AVSYNC_SIO
AVSYNC_RSTN
FSRATE2
EEPROM
IC2007
X2001
4MHz
131
INITX
STB +3.3V
126
RST_TRG
RESET SIGNAL
BUFFER
IC2006
BUFFER
IC2216
175
EEPROM_SCL
6 SCL
5 SDA
SYSTEM MUTING
SWICTH
Q2205, 2206
ERR
ANA/DIGI
• SIGNAL PATH
• R-CH is omitted due to same as L-CH.
: AUDIO (DIGITAL)
: AUDIO (ANALOG)
SYSTEM CONTROLLER
IC2003 (2/3)
SD-RAM
IC2224
LIP SYNC ADJUST
IC2223
5 DIB
4 DIA
20
DOB
19
DOA
DOD
WEN
A0 – A10, BA
DQ0 – DQ15
CSN
SI
SCLK
DMUTEN
RSTN
SIO
XCS
DOC 21
22
43
40
3
2
10
9
14
15
11
8
BCK
LRCK
14
VOUT1
46 DATA2
47 DATA3
31 DATA4
40 BCK
41 LRCK
41 LRCK
38 SCKI
33 MDO
34 MDI
DA DO
COM1_DATA
35 MC
COM1_CLK
36 ML
DA LAT
37 RST
DA RESET
13
VOUT2
LOW-PASS
FILTER
IC2222
IC2222
D/A-L
R-CH
12
VOUT3
11
VOUT4
LOW-PASS
FILTER
IC2221
IC2221
D/A-SL
R-CH
16
VOUT7
20
VOUT8
LOW-PASS
FILTER
IC2219
IC2219
D/A-SBL
R-CH
10
VOUT5
9
VOUT6
LOW-PASS
FILTER
IC2220
IC2220
D/A-C
D/A-SW
D/A CONVERTER
IC2218
14
10
45 DATA1
SD02
18
26
RX232C
TX232C
27
D232C_RX
D232C_TX
16
SD01
7 DID
6 DIC
SD04
SD03
DATA SELECTOR
IC2010
2C0 10
2C2 12
1Y 7
2C1 11
B
2
A
14
5 1C2
9 2Y
4 1C1
BCKI
MCKI
D/A MCK
RESET SWITCH
IC2004
RESET SIGNAL
GENERATOR
IC2005
CN717
(FOR SERVICE)
5
6
RS232C_MIN 134
RS232C_MOUT 135
232C-SEL2 167
232C-SEL1 166
MD2 128
BUFFER
IC2009
15
18
WE
CS
CS
170
M-D_DATA
MD_BUSY
51
M-D_INT
54
DM_BUSY
52
DSP-UCOM_MODE
50
DSP-UCOM_END-FLAG
49
DSP-UCOM_RESET
53
D-M_DATA
MD_DATA
MD_BUSY
MD_INT
DM_BUSY
MD2
DRST_TRG
DUCOM_RESET
DM_DATA
17
144
143
CASN
RASN
42
41
16
17
CAS
RAS
RAS
CLKO
CKE
30
29
35
34
CLK
CKE
CKE
DQM 31
36
14
UDQM
LDQM
LDQM
A0 – A11
DQ1 – DQ16
140 VIDEO-UCOM_VM/M
141 VIDEO-UCOM_M/VM
142 VIDEO-UCOM_BUSY
141 VIDEO-UCOM_M/VM
142 VIDEO-UCOM_BUSY
GUI_TX
STOP
GUI_RX
GUI_BUSY
124 VIDEO-UCOM_MODE
125 VIDEO-UCOM_END-FLAG
136 VIDEO-UCOM_RESET
125 VIDEO-UCOM_END-FLAG
136 VIDEO-UCOM_RESET
GUI_MD
GUI_FLG
GUI_RST
137 XM_XM/M
138 XM_M/XM
138 XM_M/XM
XM_UART_TX
XM_UART_RX
139 XM_RESET
XM RESET
3 XM_POW
XM POW
POWER RY2
75
23
148 SIRIUS_TX
149 SIRIUS_RX
149 SIRIUS_RX
SIRIUS_RX
SIRIUS_TX
77 SIRIUS-POW_EN
SI_POW_EN
25
154 DMUART_DM/M
155 DMUART_M/DM
155 DMUART_M/DM
DMPORT_TX
DMPORT_RX
156 DMPORT_DET
DMPORT_DET
19
24
22
POW-RY
STOP
82
STOP
21
CEC_M/DV
47
CEC_TX
CEC_DV/M
121
CEC_RX
20
STR-DG2100
27
27
STR-DG2100
6-4. BLOCK DIAGRAM – HDMI Section –
(Page 28)
(Page 26)
(Page 28)
(Page 32)
(Page 24)
(Page 24)
(Page 24)
(Page 24)
(Page 33)
• SIGNAL PATH
: AUDIO (DIGITAL)
: VIDEO
VIDEO SYSTEM CONTROLLER
IC3610 (1/2)
CN3501
HDMI
ASSIGNABLE
(INPUT ONLY)
IN 3
CN3502
HDMI
ASSIGNABLE
(INPUT ONLY)
IN 2
CN3503
HDMI
ASSIGNABLE
(INPUT ONLY)
IN 1
R0X0+
R0X0-
R0X0-
R0X1+
R0X1-
R0X1-
R0X2+
R0X2-
R0X2-
R0XC+
R0XC-
R0XC-
R1X0+
R1X0-
R1X0-
R1X1+
R1X1-
R1X1-
R1X2+
R1X2-
R1X2-
R1XC+
R1XC-
R1XC-
R2X0+
R2X0-
R2X0-
R2X1+
R2X1-
R2X1-
R2X2+
R2X2-
R2X2-
R2XC+
R2XC-
R2XC-
22
21
7
9
25
24
4
6
28
27
1
3
19
18
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA2+
DATA2–
CLOCK+
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
HDMI INPUT
SELECT
IC3503
GATE
IC3524(1/3)
DSDA0
30
HPD0
16
RPWR0
32
DSCL0
31
42
41
7
9
45
44
4
6
48
47
1
3
39
38
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA2+
DATA2–
CLOCK+
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
DSDA1
50
19
HPD1
36
DSCL1
51
62
61
7
9
65
64
4
6
68
67
1
3
59
58
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA2+
DATA2–
CLOCK+
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
DSDA2
70
HPD2
56
DSCL2
71
HDMI RECEIVER
IC3511
HDMI
TRANSCEIVER
IC3513
10
11
40
39
TX0+ 7
TX0-
TX0-
TX1+
TX1-
TX2+
TX2-
TXC+
TXC-
8
44
43
4
5
48
47
1
2
52
R0XC+
R0XC–
R0X0+
R0X0–
R0X1+
R0X1–
R0X2+
R0X2–
DSDA0
DSCL0
51
33
R0PWR5V
35
34
CSDA
CSCL
26
27
TSCL 78
TSDA 77
LSDA/EPSEL[0] 14
LSCL/EPSEL[1] 15
HPDIN 76
TPWR/I2CADDR 79
RESET# 13
9185_HPD[1]
9185_RST[1]
9185_HPD[1]
9185_RST[1]
93
94
9185 1 HPD1-3
9185 1 RST
DATA SELECTOR
IC3508
EEPROM
IC3509
2Y1
5
1Y1
14
3
2-COM
13
1-COM
5
SDA
6
SCL
10
A
7
WP
8
TX_RST
30
TX_INT
123
UC3V_SCL
118
UC3V_SDA
UC3V_SCL
UC3V_SDA
UC3V_SCL
UC3V_SDA
UC3V_SDA,
UC3V_SCL
117
EDID SEL0
2Y0
1
1Y0
12
16 -13,10 -7,3 -1,
144,141 -138,135 -132,
129 -126,123 -120,
117 -114,111 -108
Q0 – Q35
98 -90, 86 -77
75 -67, 63 -56
D0 -D35
ODCK 5
HSYNC 20
VSYNC 21
DE
ODCK
HSYNC
VSYNC
DE
19
SPDIF 78
SD0 -SD3
4
4
4
36
MCLK 89
SCK 86
WS 85
IDCK
88
HSYNC
2
VSYNC
3
DE
1
81 -84
SPDIF
DL0, DR1,
DL1, DR2
DL1, DR2
4
DL2
21
SD0 -SD3
MCLK
5
SCK
11
WS
10
DCLK
15
DR0
16
9 – 6
17 – 20
TX0+ 34
TX0– 33
TX0– 33
7
9
TX1+ 37
TX1– 36
TX1– 36
4
6
TX2+ 40
TX2– 39
TX2– 39
1
3
TXC+ 31
TXC– 30
TXC– 30
10
HPD
DATA0+
DATA0–
DATA1+
DATA1–
DATA2+
DATA2–
CLOCK+
CLOCK–
SDA (5V)
SCL (5V)
HOT PLUG DET
CEC
51
19
12
16
15
13
DSDA 47
DSCL 46
INT 24
RESET# 25
CSDA 49
CSCL 48
CEC DATA
SWITCH
Q2001 – 2004
CN3511
HDMI
ASSIGNABLE
(INPUT ONLY)
OUT
TX_INT
TX_RST
TX_INT
TX_RST
CEC_RX
SPDIF
WS
MCK
SCK
SD0 -SD3
95
94
XTALIN
XTALOUT
X3501
28.322MHz
28
29
CEC_TX
20
Q [4 – 11, 16 – 23, 28 – 35]
ODCK, HSYNC, VSYNC, DE
ODCK, HSYNC, VSYNC, DE
Q [4] - Q [11],
Q[16] -Q[23],
Q[28]-Q[35]
LEVER SHIFT
Q3501
GATE
IC3524(2/3)
RPWR1
52
LEVER SHIFT
Q3502
GATE
IC3524(3/3)
RPWR2
72
LEVER SHIFT
Q3503
12
13
13
11
2
1
1
3
9
10
8
19
19
RX_RST
35
AUDIO MUTE REQ
98
RX_INT
121
V.SYNC_DET
168
MUTE 67
RESET 89
INT
RESET
RX_INT
RESET
RX_INT
91
2
4
A0
3 B0
5 A1
6 B1
11 A2
10 B2
14 A3
13 B3
Y0
7
Y1
Y2
S
1
HDMI/XM SELECTOR
IC2228
9
Y3 12
SPDIF
HDMI_SPDIF
HDMI_LRCK
HDMI_MCK
HDMI_BCK
WS
XMFS
MCK
XM256FS
SCK
XM64FS
2
4
A0
3 B0
5 A1
6 B1
11 A2
B2
14 A3
B3
Y0
7
Y1
Y2
S
7
HDMI/XM SELECTOR
IC2231
9
Y3 12
SD0
XMDATA
HDMI_DATA1
HDMI_DATA2
HDMI_DATA3
HDMI_DATA4
XM/H_SEL
HDMI_ERROR
SD2
SD3
SD1
10
13
LEVEL SHIFT
IC2227
BUFFER
IC3855
XMDATA, XMFS,
XM256FS, XM64FS
7
8
1
30
2
31
TX 5VPWR
TX_5VPWR
31
STR-DG2100
28
28
STR-DG2100
6-5. BLOCK DIAGRAM – VIDEO PROCESS Section –
(Page 27)
(Page 31)
(Page 31)
(Page 26)
(Page 26)
(Page 31)
(Page 27)
(Page 31)
(Page 24)
VIDEO SYSTEM CONTROLLER
IC3610 (2/2)
VIDEO PROCESSOR
IC3601
YAMAHA WAIT_N
Faroudja UCOM BUSY
142
FSCLKP
D5
FSCLKN
C5
FLASH MEMORY
IC3615
SD-RAM
IC3618
A3P AF4
C1P AC1
B1P AC2
A1P AB1
CVBS
IPCLK2 M4
BHS L3
BVS L2
DOTCLK
HCSYNC_N
VSYNC_N
BHREF_DE K1
MSTR1_SDA
BLANK_N
Q [4 – 11,
16 – 23,
28 – 35]
16 – 23,
28 – 35]
COMP-Y
CB
CR
AND
GATE
IC3609
BUFFER
IC3620
PD0 – PD23
L23 – L26, N23 – N26,
K23 – K26, J23, J24, G23 –G26,
F23 – F26, E23, E24
DCLK
P24
DHS
P25
DVS
R26
ODCK
HSYNC
VSYNC
DEN
P26
DE
B26
C26
XTAL
TCLK
X3603
19.6MHz
F_D [0] – F_D [15]
F_A [1] – F_A [21]
FSDATA [16] – FSDATA [31]
FSADD [0] – FSADD [12]
FSADD [0] – FSADD [12]
FSCKE
C4
FSBKSEL0
C21
FSBKSEL1
C20
FSCS0
D21
FSRAS
C24
FSCAS
D24
FSWE
C23
FSDQM3
B22
FSDQM2
B17
FSDQS3
A22
45
46
44
26
27
24
23
22
21
20
47
16
A17
CLK
/CLK
CKE
BA0
BA1
CS
RAS
CAS
WE
LDM
UDM
LDQS
UDQS
CLK
/CLK
CKE
BA0
BA1
CS
RAS
CAS
WE
LDM
UDM
LDQS
UDQS
51
ROM_CS_N AD24
OCN_RE_N AC25
OCN_WE_N AC26
26
28
11
CE
OE
OE
WE
12 RESET
FSDQS2
SD-RAM
IC3602
FSDATA [0] – FSDATA [15]
CLKP
CLKN
CKE
FSBKSEL0
FSBKSEL1
FSCS0
RAS
CAS
WE
CLKP
CLKN
CKE
FSBKSEL0
FSBKSEL1
FSCS0
RAS
CAS
WE
FSDQM1
A11
FSDQM0
A6
FSDQS1
B11
45
46
44
26
27
24
23
22
21
20
47
16
B6
51
FSDQS0
BDATA21
I
BDATA16
BDATA13
I
BDATA8
BDATA5
I
BDATA0
J1 – J3,
H1 – H3
G3, F1 – F3,
E1, E2
D2, D3,
C1 – C3, B1
DR0 – DR5
DG0 – DG5
DB0 – DB5
111 – 116
DR0 – DR5
119 – 124
DG0 – DG5
127 – 132
DB0 – DB5
139
137
136
138
DOTCLK
HCSYNC_N
VSYNC_N
VSYNC_N
BLANK_N
WAIT_N
23
YAMAHA INT_N
INT_N
25
YAMAHA RESET
YAMAHA CE
RESET_N
39
CS_N
28
WR_N
29
RD_N
30
Faroudja Power DETECT
125
MSTR1_SCL A3
Faroudja UCOM UART TX
141
OCM_UDI_1 B3
Faroudja UCOM UART RX
140
OCM_UDO_1 B2
Faroudja UCOM RESET
126
RESET AD9
119
22
21
15 – 22
D0 – D7
46 – 56, 59 – 63
SRAM IO0 – SRAM IO15/
YAMAHA D0 – YAMAHA D7
67 – 72, 75 – 83, 64 – 66
SRAM A0 – SRAM A16/
YAMAHA PS0 – YAMAHA PS2
33 – 31
PS0 – PS2
DIR
1
XOE
19
18
BUFFER
IC3619
XDE
19
YAMAHA_D [0] –
YAMAHA_D [7]
YAMAHA_D [7]
YAMAHA_A [0] –
YAMAHA_A [2]
YAMAHA_A [2]
SRAM CE
CE
6
19
SRAM LB/WE
1
26
SRAM UB/WE
2
27
RDX
25
3
10 9
8
12 13
11
17
40
39
WE
UB
LB
41
OE
Flash Update RX 134
Flash Update TX 135
MAIN UCOM UART RX
137
MAIN UCOM UART TX
138
MAIN UCOM UART BUSY
139
D [8] – D [15]
D [0] – D [15]
D [0] – D [15]
A [0] – A [2]
A [0] – A [17]
A [1] – A [17]
RX232C
TX232C
GUI_RX
GUI_TX
GUI_BUSY
STOP IN
6
INITX
131
STOP
GUI_RST
ENDFLAG
136
GUI_FLG
MD2
128
GUI_MD
FLASH MEMORY
IC3603
EEPROM
IC3621
34
13
74
73
OE
WE
MOE_N
MWE_N
Y_D [0] – Y_D [15]
Y_A [0] – Y_A [23]
OSD CONTROLLER
IC3604
142
141
XOUT
XIN
X3601
33.2MHz
39
40
X0
X1
X3602
4MHz
S-RAM
IC3611
IC3611
DATA BUS
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS
BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
14 RESET
33
22
27
32
UC3V_SCL
UC3V_SDA
44
23 P_HSYNC
50 S_HSYNC
24 P_VSYNC
49 S_VSYNC
V
Y/G
SDA
21
SCLK
22
RESET
33
39
VOUT
Y OUT
CB/R 38
CB OUT
CR/B 37
CR OUT
HSYNC
Q [16 – 23,
28 – 35]
28 – 35]
VSYNC
DE
ODCK
DAC_CLK_SEL
VDAC_RESET
4 – 9, 12, 13,
16 – 18, 26 – 30
Y0 – Y7, C0 – C7
25 P_BLANK
48 S_BLANK
32 CLKIN_A
FREQUENCY
MULTIPLIER
IC3854
D/A CONVERTER
IC3850
2
8
4
IN
OUT2
FSO
35
34
VDAC_RESET
32
DAC CLK SEL
7
DAC_CLK_SEL
VDAC_RESET
Q [4 – 11, 16 – 23,
28 – 35],
ODCK, HSYNC,
VSYNC, DE
28 – 35],
ODCK, HSYNC,
VSYNC, DE
24
16
28
UC3V_SDA,
UC3V_SCL
29
• SIGNAL PATH
: VIDEO
A2
MSTR0_SDA AA23
SDA
5
MSTR0_SCL AA24
SCL
6
DQ0 – DQ15
A0 – A12
DQ0 – DQ15
A0 – A20
I/O0 –
I/O15
A0 –
A16
DQ0 – DQ15
A0 – A12
OCMDATA0 –
OCMDATA15
OCMADDR1 –
OCMADDR21
DQ0 – DQ15
A0 – A23
MD0 – MD15
MA1 – MA24
NON LPCM
92
NON_LPCM
15
Click on the first or last page to see other STR-DG2100 service manuals if exist.