Sony STR-DE915 / TA-V909 / TA-VE910 Service Manual ▷ View online
— 65 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
—
—
I
I
I
I
I
O
O
O
I
O
O
O
O
I
O
O
O
O
O
O
I
I
O
I
I
—
—
O
O
—
—
O
O
O
O
O
O
—
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Ground
+5V power supply
System reset input “L” : reset
Oscillation control signal input “H” : ON
Test pin (Connected to ground)
Test pin (Connected to ground)
Test pin (Connected to ground)
Test pin (Open)
Test pin (Open)
Test pin (Open)
Test pin (Connected to ground)
Test pin (Open)
Test pin (Open)
Test pin (Open)
Test pin (Open)
Test pin (Connected to ground)
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Test pin (Connected to ground)
Test pin (Connected to ground)
Test pin (Open)
Test pin (Connected to ground)
Test pin (Connected to ground)
Ground
+5V power supply
Address data output to SRAM
Address data output to SRAM
Ground
+5V power supply
Address data output to SRAM
Address data output to SRAM
Write enable signal output to SRAM “L” : active
Address data output to SRAM
Address data output to SRAM
Address data output to SRAM
Ground
Address data output to SRAM
Output enable output to SRAM
Address data output to SRAM
Data bus input/output with SRAM
Data bus input/output with SRAM
Data bus input/output with SRAM
Data bus input/output with SRAM
Data bus input/output with SRAM
Data bus input/output with SRAM
Data bus input/output with SRAM
Pin Name
GND
VDD
RESET
OSCON
DATA
MCK
MLTB
IDST
IDCK
IDO
TM0
ECCK
DEN
DRY
MSYC
TM1
A0
A1
A2
A3
A4
A5
TM2
TM3
XOUT
XIN
XENT
GND
VDD
A6
A7
GND
VDD
A12
A14
WE
A13
A8
A9
GND
A11
OE
A10
D7
D6
D5
D4
D3
D2
D1
• IC3308 DOLBY AC-3 demodulator (SN-PM4007A)
— 66 —
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
—
—
I
I
O
I
I
I
I
O
O
O
I
I
O
I
O
O
O
I
I
I
O
O
O
O
I
—
—
—
I
I
—
I
—
I
O
O
O
—
O
O
O
O
O
I
I
—
—
Description
Data bus input/output with SRAM
+5V power supply
Ground
Test pin (Connected to VDD)
VCXO input (18.432MHz)
VCXO output (18.432MHz)
Test pin (Connected to Ground)
Test pin (Connected to Ground)
Test pin (Connected to Ground)
Test pin (Connected to Ground)
Test pin (Open)
Test pin (Open)
Output of internal phase comparator (3 state)
Test pin (Connected to Ground)
PDO output control input “L” : output ON
Mute signal output “H” : mute
Test pin (Connected to Ground)
Test pin (Open)
Test pin (Open)
Digital-out signal output (Serial data stream output)
Dgital external input
Through out to DAOUT when DASEL is “H” (Not used)
Digital-out selection input (Not used)
Test pin (Connected to Ground)
C2 error correction state display
Outputs if corrected properly (Not used)
C2 error correction state display
Outputs number of errors at C2 (Not used)
C2 error correction state display
Outputs whether error is present at C1 (Not used)
C2 error correction state display
Outputs number of errors at C1 (Not used)
Muting input “H” mute
+5V power supply
Ground
+5V power supply (Analog)
Comparator input (+) (QPSK input)
Comparator input (–)
Ground (Analog)
Test pin (Connected to ground)
+5V power supply
Test pin (Connected to ground)
Comparate output
Comparate inverted output
9.216MHz output (Open)
Ground
Test pin (Connected to ground)
Test pin (Connected to ground)
Test pin (Connected to ground)
Test pin (Connected to ground)
Test pin (Connected to ground)
Test pin (Open)
Test pin (Open)
Ground (Analog)
+5V power supply (Analog)
Pin Name
D0
VDD
GND
TI1
VIN
VOUT
TI2
TI3
TLD8
TCK
TRP
TD0
PD0
TI4
PDDIS
MUTO
TI5
VLDY
DASYO
DAOUT
DAIN
DASEL
TI8
C2F1
C2F0
C1F1
C1F0
MUTI
VDD
GND
AVDD
CPIN
CMIN
AGND
TM4
VDD
DIN
DOUT
DOUTB
C9M
GND
WINGT
SYST0
SYST1
ADST0
ADST1
TM5
BUNRI
AGND
AVDD
— 67 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O
I
I
O
—
I
I
O
—
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
Description
Data input with built-in amplifier (Responding to the coaxial optical module)
Data input (Responding to the optical module)
Emphasis, input bi-phase, validity flag output
Power supply (+5V)
VCO gain control input (Fixed at “H”)
VCO freerunning frequency setting input
LPF setting of PLL (Fixed at “L”)
Ground
System clock select input (384fs, 512fs) (Connected to the power supply.)
Reset input
Clock input for preventing PLL lock failure
Test input (Normally “L”)
Microcomputer IF clock input
Microcomputer IF latch/chip enable input
Microcomputer IF write data input
Microcomputer IF read data output
Microcomputer IF Sub-Q sync and ID sync output (Not used)
VCO clock output (Freerunning, 384fs, 512fs) (Not used)
128fs clock output (Not used)
Bit clock output
L/R clock output
Audio data output
PLL lock error mute output
Pin Name
DIN1
DIN2
E/DOUT
VDD
R
VIN
VCO
GND
CKSEL
XMODE
AVOCK
TST1
TST2
SCLK
XLAT
SWDT
SRDT
DQSY
CKOUT
FS128
BCK
LRCK
DATAO
EROR
• IC3311 Digital Audio Interface Receiver (CXD8521M)
— 68 —
• IC3410 Digital Signal Processor (DSP56009FJ88F)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
—
O
O
O
O
—
O
—
—
—
O
O
O
O
—
O
—
O
O
O
—
O
O
O
O
I
I
—
—
I
—
I
—
—
I
I
I
I
I
—
Description
Address buffer ground
Chip select 0 output to S-RAM (Not used)
Chip select 3 output to S-RAM (Not used)
Address data output to S-RAM (Not used)
Address bus buffer power supply (+5V)
Address data output to S-RAM(Not used)
Ground for address bus buffer
Power supply for internal logic (+5V)
Ground for internal logic
Address data output to S-RAM (Not used)
Ground for address bus buffer
Address data output to S-RAM (Not used)
Power supply for address bus buffer (+5V)
Address data output to S-RAM (Not used)
Ground for address bus buffer
Address data output to S-RAM (Not used)
SPI serial clock signal input from system controller
External frequency input (3 MHz)
Power supply for internal logic (+5V)
Ground for internal logic
PLL initialize input (Fixed at “L”)
Ground for PLL
PLL filter input (Connected to 0.01 µF capacitor)
Power supply for PLL (+5V)
Ground for serial port
Master data signal input from system controller
Reset signal input from system controller
Mode select A (Fixed at “H”)
Mode select B (Fixed at “L”)
Mode select C (Fixed at “H”)
Power supply for serial port (+5V)
Pin Name
AGND
MCS0
MCS3
MA14
MA13
AVCC
MA12
AGND
QVCC
QGND
MA11
MA10
MA9
MA8
AGND
MA7
AVCC
MA6
MA5
MA4
AGND
MA3
MA2
MA1
MA0
SCK
EXTAL
QVCC
QGND
PINIT
PGND
PCAP
PVCC
SGND
MISO
RESET
MODA
MODB
MODC
SVCC
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