Sony STR-DE885 / STR-DE985 Service Manual ▷ View online
13
STR-DE885/DE985
SECTION 4
DIAGRAMS
1
VSS
—
Ground
2
XRST
I
Reset signal input
3
EXTIN
I
Not used (connected to ground)
4
FS2
I
Sampling frequency select signal input (connected to ground)
5
VDDI
—
Power supply pin (+2.5 V)
6
FS1
I
Sampling frequency select signal input (connected to ground)
7
PLOCK
O
Internal PLL lock signal output (Not used (open))
8
VSS
—
Ground
9
MCLK1
I
System clock signal input (13.5 MHz)
10
VDDI
—
Power supply pin (+2.5 V)
11
VSS
—
Ground
12
MCLK2
O
System clock signal output (13.5 MHz)
13
MS
I
Master/slave operation select signal input (L : internal clock, H : EXTIN clock)
14
SCKOUT
O
Serial clock signal output
15
LRCKI1
I
L/R sampling clock signal input (Not used (open))
16
VDDE
—
Power supply pin (+3.3 V)
17
BCKI1
I
Bit clock signal input (Not used (open))
18
SDI1
I
Audio serial data input
19
LRCKO
O
L/R sampling clock signal output
20
BCKO
O
Bit clock signal output
21
VSS
—
Ground
22
KFSIO
I/O
Audio clock signal (384fs/256fs) input/output
23 to 26
SDO1 to SDO4
O
Audio serial data output
27
SPDIF
O
S/PDIF output (Not used (open))
28
LRCKI2
I
L/R sampling clock signal input
29
BCKI2
I
Bit clock signal input
30
SDI2
I
Audio serial data input
31
VSS
—
Ground
32
HACN
O
Host acknowledge signal output
33
HDIN
I
Host serial data input
34
HCLK
I
Host clock signal input
35
HDOUT
O
Host serial data output
36
HCS
I
Host chip select input
37
SDCLK
O
Not used (open)
38
CLKEN
O
Not used (open)
39
RAS
O
Row address strobe signal output (Not used (open))
40
VDDI
—
Power supply pin (+2.5 V)
41
VSS
—
Ground
42
CAS
O
Column address strobe signal output (Not used (open))
43
DQM/OE0
O
Not used (open)
44
CS0
O
Chip select signal output
45
WE0
O
Write enable signal output
46
VDDE
—
Power supply pin (+3.3 V)
47
WMD1
I
External memory wait mode setting signal input (connected to H)
48
VSS
—
Ground
49
WMD0
I
External memory wait mode setting signal input (connected to ground)
50
PAGE2
O
External memory page select signal output (Not used (open))
51
VSS
—
Ground
52, 53
PAGE1, PAGE0
O
External memory page select signal output (Not used (open))
54
BOOT
I
Boot mode control signal input (connected to ground)
55
BTACT
O
Boot mode display signal output (Not used (open))
4-1. IC PIN DESCRIPTIONS
• IC1501 CXD9617R (AUDIO DSP1) (DIGITAL Board (2/4))
Pin No.
Pin Name
I/O
Pin Description
14
STR-DE885/DE985
56
BST
I
Boot stop signal input
57
MOD1
I
Mode select signal input (L : 384fs, H : 256fs)
58
MOD0
I
Mode select signal input (L : single chip mode, H : use prohibited)
59
EXLOCK
I
External lock signal input
60
VDDI
—
Power supply pin (+2.5 V)
61
VSS
—
Ground
62, 63
A17, A16
O
Address signal output (Not used (open))
64 to 66
A15 to A13
O
Address signal output (SRAM)
67
GP10
O
L/R sampling clock signal output
68
GP9
O
GP9 signal output
69
GP8
I
Audio signal input
70
VDDI
—
Power supply pin (+2.5 V)
71
VSS
—
Ground
72 to 75
D15/GP7 to D12/GP4
I/O
External memory data input/output (general port)
76
VDDE
—
Power supply pin (+3.3 V)
77 to 80
D11/GP3 to D8/GP0
I/O
External memory data input/output (general port)
81
VSS
—
Ground
82
A9
O
Address signal output (SRAM)
83 to 85
A12 to A10
O
Address signal output (SRAM)
86
TDO
O
Emulation data output (Not used (open))
87
TMS
I
Emulation start/end select data input (Not used (open))
88
XTRST
I
Emulation break signal input (Not used (open))
89
TCK
I
Emulation clock signal input (Not used (open))
90
TDI
I
Emulation data input (Not used (open))
91
VSS
—
Ground
92 to 97
A8 to A3
O
Address signal output (SRAM)
98, 99
D7, D6
I/O
External memory data input/output (SRAM)
100
VDDI
—
Power supply pin (+2.5 V)
101
VSS
—
Ground
102 to 105
D5 to D2
I/O
External memory data input/output (SRAM)
106
VDDE
—
Power supply pin (+3.3 V)
107, 108
D1, D0
I/O
External memory data input/output (SRAM)
109, 110
A2, A1
O
Address signal output (SRAM)
111
VSS
—
Ground
112
A0
O
Address signal output (SRAM)
113
PM
I
PLL initialization signal input
114, 115
SDI3, SDI4
I
Audio serial data input (Not used (open))
116
SYNC
I
Sync/unsync select signal input (L : sync, H : unsync)
117 to 119
VSS
—
Ground
120
VDDI
—
Power supply pin (+2.5 V)
Pin No.
Pin Name
I/O
Pin Description
15
STR-DE885/DE985
1
VDDI
—
Power supply pin (+2.5 V)
2
EXTIN
I
Not used (connected to ground)
3, 4
WMD1, WMD0
I
External memory wait mode setting signal input (connected to H)
5
MOD1
I
Mode select signal input (L : 384fs, H : 256fs)
6
MOD0
I
Mode select signal input (L : single chip mode, H : use prohibited)
7
VSS
—
Ground
8
XRST
I
Reset signal input
9
VSS
—
Ground
10
SCKOUT
O
Serial clock signal output
11
VDDI (PLL)
—
Power supply pin (+2.5 V) (for PLL)
12
SYNC
I
Sync/unsync select signal input (L : sync, H : unsync)
13 to 15
PAGE2 to PAGE0
O
External memory page select signal output (Not used (open))
16
PLOCK
O
Internal PLL lock signal output
17
BTACT
O
Boot mode display signal output (Not used (open))
18
VDDE
—
Power supply pin (+3.3 V)
19
VSS
—
Ground
20 to 22
D31 to D29
I/O
External memory data input/output (SRAM)
23
A17
O
Address signal output (Not used (open))
24
VSS
—
Ground
25, 26
SDO3, SDO4
O
Audio serial data output
27, 28
SDI1, SDI2
I
Audio serial data input
29
LRCKI1
I
L/R sampling clock signal input
30
VSS
—
Ground
31, 32
D28, D27
I/O
External memory data input/output (SRAM)
33
A16
O
Address signal output (Not used (open))
34
A15
O
Address signal output (SRAM)
35
SDI3
I
Audio serial data input
36
L2
O
Not used (open)
37
VDDI
—
Power supply pin (+2.5 V)
38
BCKI1
I
Bit clock signal input
39
SDI4
I
Audio serial data input
40
MS
I
Master/slave operation select signal input (L : internal clock, H : EXTIN clock)
41, 42
A14, A13
O
Address signal output (SRAM)
43, 44
D26, D25
I/O
External memory data input/output (SRAM)
45
VSS
—
Ground
46
BCKI2
I
Bit clock signal input (Not used (open))
47, 48
FS2, FS1
I
Sampling frequency select signal input (connected to ground)
49
SPDIF
O
S/PDIF output (Not used (open))
50
A12
O
Address signal output (SRAM)
51 to 53
D24 to D22
I/O
External memory data input/output (SRAM)
54
VDDE
—
Power supply pin (+3.3 V)
55
VSS
—
Ground
56 to 58
D21 to D19
I/O
External memory data input/output (SRAM)
59
A11
O
Address signal output (SRAM)
60, 61
SDO1, SDO2
O
Audio serial data output
62
KFSIO
I/O
Audio clock signal (384fs/256fs) input/output
63
LRCKO
O
L/R sampling clock signal output
64
BCKO
O
Bit clock signal output
65
VDDI
—
Power supply pin (+2.5 V)
66
VSS
—
Ground
67, 68
D18, D17
I/O
External memory data input/output (SRAM)
69, 70
A10, A9
O
Address signal output (SRAM)
• IC1551 CXD9616R (AUDIO DSP2) (DIGITAL Board (3/4))
Pin No.
Pin Name
I/O
Pin Description
16
STR-DE885/DE985
71
CAS
O
Column address strobe signal output
72
RAS
O
Row address strobe signal output
73
VDDI
—
Power supply pin (+2.5 V)
74
HDIN
I
Host serial data input
75
HCLK
I
Host clock signal input
76
HCS
I
Host chip select input
77, 78
A8, A7
O
Address signal output (SRAM)
79
D16
I/O
External memory data input/output (SRAM)
80
D15
I/O
External memory data input/output (SRAM) (Not used (open))
81
VSS
—
Ground
82
HDOUT
O
Host serial data output
83
HACN
O
Host acknowledge signal output
84
CS0
O
Chip select signal output
85
WE0
O
Write enable signal output
86
A6
O
Address signal output (SRAM)
87 to 89
D14 to D12
I/O
External memory data input/output (SRAM) (Not used (open))
90
VDDE
—
Power supply pin (+3.3 V)
91
VSS
—
Ground
92 to 94
D11 to D9
I/O
External memory data input/output (SRAM) (Not used (open))
95
A5
O
Address signal output (SRAM)
96
VDDI
—
Power supply pin (+2.5 V)
97
TCK
I
Emulation clock signal input (Not used (open))
98
TDI
I
Emulation data input (Not used (open))
99
TDO
O
Emulation data output (Not used (open))
100
TMS
I
Emulation start/end select data input (Not used (open))
101
XTRST
I
Emulation break signal input (Not used (open))
102
VSS
—
Ground
103, 104
D8, D7
I/O
External memory data input/output (SRAM) (Not used (open))
105, 106
A4, A3
O
Address signal output (SRAM)
107, 108
GP10, GP9
—
Not used (open)
109
VDDI
—
Power supply pin (+2.5 V)
110
GP8
—
Not used (open)
111
GP7
I
Serial clock signal input
112
GP6
—
Not used (open)
113, 114
A2, A1
O
Address signal output (SRAM)
115, 116
D6, D5
I/O
External memory data input/output (SRAM) (Not used (open))
117
VSS
—
Ground
118, 119
GP5, GP4
—
Not used (open)
120
GP3
O
Error signal output
121
NC
—
Not used (open)
122
A0
O
Address signal output (SRAM)
123 to 125
D4 to D2
I/O
External memory data input/output (SRAM) (Not used (open))
126
VDDE
—
Power supply pin (+3.3 V)
127
VSS
—
Ground
128, 129
D1, D0
I/O
External memory data input/output (SRAM) (Not used (open))
130
GP2
—
Not used (open)
131
GP1
I
Clock signal input
132
GP0
I
Serial clock signal input
133
SDCLK
O
Not used (open)
134
CLKEN
O
Not used (open)
135
DQM
O
Not used (open)
136
EXLOCK
I
External lock signal input
Pin No.
Pin Name
I/O
Pin Description
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