Sony STR-DE845 / STR-DE945 Service Manual ▷ View online
49
Pin No.
Pin Name
I/O
Description
56
SDATA
O
Tuner data output to the FM/AM tuner unit (TM301)
57
SCLK
O
Tuner clock signal output to the FM/AM tuner unit (TM301)
58
DATA IN
I
PLL data input from the FM/AM tuner unit (TM301)
59
AUSTOP
I
Tuned display detection signal input from the FM/AM tuner unit (TM301)
60
STEREO
I
Stereo detection signal input from the FM/AM tuner unit (TM301)
61, 62
NC
I
Not used (fixed at “L”)
63
VSS
—
Ground terminal
64
NC
I
Not used (fixed at “L”)
65
TH
I
Protect signal input terminal (fixed at “L” in this set)
66
PROTEC
I
Over load detect signal input from the protect circuit “L”: protect detect
67
STOP
I
AC power check signal input from the power control (IC1206)
68 to 71
NC
I
Not used (fixed at “L”)
72
VIDEO (SW4)
O
Video select (SW4) signal output to the video select switch (IC251, 252)
73
X1A
—
Not used (open)
74
X0A
—
Not used (open)
75
VIDEO (SW3)
O
Video select (SW3) signal output to the video select switch (IC251, 252)
76
VIDEO (SW2)
O
Video select (SW2) signal output to the video select switch (IC251, 252)
77
VIDEO (SW1)
O
Video select (SW1) signal output to the video select switch (IC251, 252)
78
HI-FI/QS
I
Model check detection input terminal “L”: HI-FI “H”: QS
79
TAPE NO/YES
I
Tape no/yes signal detection input terminal “L”: tape yes “H”: tape no
80
VIDEO 3 NO/YES
I
VIDEO 3 no/yes signal detection input terminal “L”: VIDEO 3 yes “H”: VIDEO 3 no
81
DTS NO/YES
I
DTS no/yes signal detection input terminal “L”: DTS yes “H”: DTS no
82
ACMUTE
O
Muting control signal output to the power amp (IC501, 601, 701)
83
96K NO/YES
I
96K no/yes signal detection input terminal Not used
84
TMUTE
O
Tuner muting control signal output to the FM/AM tuner unit (TM301) “H”: muting
85
SMUTE
O
Surround muting control signal output to the AF amp (IC1508, 1509, 1510)
86
HSTX
—
Hardware standby terminal (fixed at “H” in this set)
87
MD2
O
MD2 signal output to the display controller (IC102)
88
MD1
O
MD1 signal output terminal (fixed at “H” in this set)
89
MD0
O
MD0 signal output to the display controller (IC102)
90
REST
I
Reset signal input from the display controller (IC102)
91
VSS
—
Ground terminal
92
XO
O
Main system clock output terminal (16MHz)
93
XI
I
Main system clock input terminal (16MHz)
94
VCC
—
Power supply terminal (+5V)
95, 96
PO0, PO1
I
Rewrite terminal for the flash memory Not used (fixed at “L”)
97
RY-4/8
O
4/8 relay drive signal out put terminal Not used (open)
98
RY-PRE
O
Pre amp relay drive signal output terminal “H”: relay on
99
RY-FRONT/A
O
Front speaker A relay drive signal output terminal “H”: relay on
100
RY-FRONT/B
O
Front speaker B relay drive signal output terminal “H”: relay on
101
RY-CENTER
O
Center speaker relay drive signal output terminal “H”: relay on
102
RY-REAR
O
Rear speaker relay drive signal output terminal “H”: relay on
103
RY-WOOFER
O
Rear woofer relay drive signal output terminal “H”: relay on
104
RY-HP
O
Headphone relay drive signal output terminal “H”: relay on
105
RY-POWER
O
Power relay drive signal output terminal “H”: relay on
106
ANG/DIG
O
Analog/digital select signal output terminal “L”: analog “H”: digital
50
Pin No.
Pin Name
I/O
Description
107
DIG-INB
O
Digital input select B control signal output to the select switch (IC1005)
108
DIG-INA
O
Dgital input select A control signal output to the select switch (IC1005)
109
XMODE
O
Reset signal output to the digital audio interface receiver (IC1101)
110
CL
O
Clock signal output to the digital audio interface receiver (IC1101)
111
CE
O
Chip enable signal output to the digital audio interface receiver (IC1101)
112
DI
O
Data output to the digital audio interface receiver (IC1101)
113
DO
I
Data input from the digital audio interface receiver (IC1101)
114
ERROR
I
Error signal input from the digital audio interface receiver (IC1101)
115 to
111
NC
I
Not used (fixed at “L”)
118
XSTATE
I
Clock status flag signal input from the digital audio interface receiver (IC1101)
119
VSS
—
Ground terminal
120
NC
I
Not used (fixed at “L”)
51
• DIGITAL BOARD IC1401 CXD2712R (AUDIO DSP)
Pin No.
Pin Name
I/O
Description
1
VSS3
—
Ground terminal
2 to 5
SOA to SOD
O
Serial data output to the A/D, D/A converter
6, 7
ECJ0, ECJ1
I
Conditional jump input terminal (fixed at “L” in this set)
8
NC
O
Not used (fixed at “L”)
9
XHDWR
I
Write data input from the system controller (IC1201)
10
XHDRD
I
Read data input terminal Not used (fixed at “H”)
11
VSS4
—
Ground terminal
12
VDD2
—
Power supply terminal (+3.3V)
13
HRDY
O
Ready signal output to the system controller (IC1201)
14
XHDCS
I
Chip select signal input from the system controller (IC1201)
15
HA0
I
Address signal input from the system controller (IC1201)
16 to 20
HD0 to HD4
I/O
Two-way data bus with the system controller (IC1201)
21
VSS5
—
Ground terminal
22
VDD3
—
Power supply terminal (+3.3V)
23 to 25
HD5 to HD7
I/O
Two-way data bus with the system controller (IC1201)
26
XRST
I
Reset signal input from the system controller (IC1201) “L”: reset
27 to 30
FGP0 toFGP3
I/O
Data output terminal for the test
31
VSS6
—
Ground terminal
32 to 40
ED0 to ED8
I/O
Two-way data bus with external RAM Not used (fixed at “L”)
41
VSS7
—
Ground terminal
42
VDD4
—
Power supply terminal (+3.3V)
43 to 49
ED9 to ED15
I/O
Two-way data bus with external RAM Not used (fixed at “L”)
50
TEST
I
Test terminal (Normally: fixed at “L”)
51
VSS8
—
Ground terminal
52
VDD5
—
Power supply terminal (+3.3V)
53 to 60
ED16 to ED23
I/O
Two-way data bus with the S-RAM (IC1402)
61
VSS9
—
Ground terminal
62 to 69
ED24 to ED31
I/O
Two-way data bus with the S-RAM (IC1402)
70
XOE
O
Output enable signal output to the S-RAM (IC1402)
71
VSS10
—
Ground terminal
72
VDD6
—
Power supply terminal (+3.3V)
73
CAS
O
External RAM column address strobe signal output terminal Not used
74
XWE
O
Write enable signal output to the S-RAM (IC1402)
75
RAS
O
External RAM raw address strobe signal output terminal Not used
76 to 80
EA0 to EA4
O
Address signal output to the S-RAM (IC1402) or test data input from the S-RAM (IC1402)
81
VSS11
—
Ground terminal
82
VDD7
—
Power supply terminal (+3.3V)
83 to 89
E5 to EA11
O
Address signal output to the S-RAM (IC1402) or test data input from the S-RAM (IC1402)
90
EA12
O
Address signal output to the S-RAM (IC1402)
91
VSS0
—
Ground terminal
92 to 94
EA13 to EA15
O
Address signal output to the S-RAM (IC1402)
95
EA16
O
Address signal output terminal (for check)
96
TSTA
I
Test data input terminal (Normally: fixed at “L”)
97
PLDIVF
I
PLL input frequency select terminal “L”: 256fs “H”: 128fs (fixed at “L” in this set)
98
PLDIVB
O
PLL input frequency select terminal “L”: 768fs “H”: 1024fs (fixed at “H” in this set)
52
Pin No.
Pin Name
I/O
Description
99
CLKI
I
Master clock signal input terminal (10MHz)
100
CLKO
O
Master clock signal output terminal (10MHz)
101
VSS1
—
Ground terminal
102
VDD0
—
Power supply terminal (+3.3V)
103
AVSS
—
Ground terminal (for PLL cell)
104
AVDD
—
Power supply terminal (+3.3V) (for PLL cell)
105
PLLCK
I/O
PLL output/test clock signal input terminal (for check)
106
XPLLEN
I
PLL cell oscillation enable signal input terminal “L”: oscillation enable
(fixed at “L” in this set)
(fixed at “L” in this set)
107
TST
I
Test data input terminal (Normally: fixed at “L”)
108
LRCT
I
Frequency counter input terminal (fixed at “L” in this set)
109
LROUT
O
Clock driver signal output terminal (for check)
110
BKOUT
O
Clock driver signal output terminal (for check)
111
VSS2
—
Ground terminal
112
VDD1
—
Power supply terminal (+3.3V)
113
BCK0
I
Clock 0 signal input from the digital audio interface receiver (IC1101)
114
BCK1
I
Clock 1 signal input from the digital audio interface receiver (IC1101)
115
LRCK0
I
Clock 0 signal input from the digital audio interface receiver (IC1101)
116
LRCK1
I
Clock 1 signal input from the digital audio interface receiver (IC1101)
117 to
120
SIA to SID
—
Serial data input from the dolby digital audio decoder (IC1301)
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