Sony STR-DE1015G Service Manual ▷ View online
— 41 —
Address buffer ground
Chip select 0 output to S-RAM (Not used)
Address data output to S-RAM (Not used)
Address bus buffer power supply (+5V)
Address data output to S-RAM(Not used)
Ground for address bus buffer
Power supply for internal logic (+5V)
Ground for internal logic
• IC3410 DOLBY AC-3 decoder (DSP56009FJ88)
Function
AGND
MCS0
MA15
MA14
MA13
AVCC
MA12
AGND
QVCC
QGND
MA11
MA10
MA9
MA8
AGND
MA7
AVCC
MA6
MA5
MA4
AGND
MA3
MA2
MA1
MA0
SCK/SCL
EXTAL
QVCC
QGND
PINIT
PGND
PCAP
PVCC
SGND
MISO/SDA
RESET
MODA/IRQA
MODB/IRQB
MODC/NMI
SVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
–
O
O
O
O
–
O
–
–
–
O
O
O
O
–
O
–
O
O
O
–
O
O
O
O
I
I
–
–
I
–
I
–
–
I
I
I
I
I
–
Function
Pin No.
Pin Name
I/O
Address data output to S-RAM (Not used)
Ground for address bus buffer
Address data output to S-RAM (Not used)
Power supply for address bus buffer (+5V)
Address data output to S-RAM (Not used)
Ground for address bus buffer
SPI serial clock signal input from system controller
External frequency input (3 MHz)
Power supply for internal logic (+5V)
Ground for internal logic
PLL initialize input (Fixed at “L”)
Ground for PLL
PLL filter input (Connected to 0.01 µF capacitor)
Power supply for PLL (+5V)
Ground for serial port
Master data signal input from system controller
Reset signal input from system controller
Mode select A (Fixed at “H”)
Mode select B (Fixed at “L”)
Mode select C (Fixed at “H”)
Power supply for serial port (+5V)
Address data output to S-RAM (Not used)
• Abbreviation
PLL: Phase Locked Loop
— 42 —
Function
Master data signal output to system controller
SPI slave select signal input from system controller
Host request signal input from system controller
Ground for serial port
Audio serial data 2 signal output (Not used)
Audio serial data 1 signal output
Audio serial data 0 signal output
Power supply for serial port (+5V)
Serial clock transmission
Word select transmission
Serial clock reception
Ground for internal logic
Power supply for internal logic (+5V)
Ground for serial port
Word select reception
Audio serial data 1 signal input
Audio serial data 0 signal input
Debug serial signal output (Not used)
Debug serial signal input (Not used)
Debug serial clock signal input (Not used)
Debug request input (Fixed at “H”)
MOSI/HA0
SS/HA2
HREQ
SGND
SDO2
SDO1
SDO0
SVCC
SCKT
WST
SCKR
QGND
QVCC
SGND
WSR
SDI1
SDI0
DSO
DSI/OS0
DSCK/OS1
DR
MD7
MD6
MD5
MD4
DGND
MD3
MD2
MD1
DVCC
MD0
DGND
GPIO3
GPIO2
GPIO1
GPIO0
MRD
MWR
MA15/MCS1
MA16/MCS2/MCAS
O
I
I
–
O
O
O
–
O
O
I
–
–
–
I
I
I
O
I
I
I
I/O
I/O
I/O
I/O
–
I/O
I/O
I/O
–
I/O
–
I/O
I/O
I/O
I/O
O
O
O
O
Function
Pin No.
Pin Name
I/O
Data input/output with S-RAM (Not used)
Ground for data bus buffer
Data input/output with S-RAM (Not used)
Power supply for data bus buffer (+5V)
Data input/output with S-RAM (Not used)
Ground for data bus buffer
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
General DSP input/output (Not used)
Write strobe signal output to S-RAM (Not used)
Read strobe signal output to S-RAM (Not used)
Low address strobe signal output to S-RAM (Not used)
Column address strobe signal output to S-RAM (Not used)
— 43 —
Address buffer ground
Chip select 0 output to S-RAM (Not used)
Address data output to S-RAM
Address bus buffer power supply (+5V)
Address data output to S-RAM
Ground for address bus buffer
Power supply for internal logic (+5V)
Ground for internal logic
Function
AGND
MCS0
MA15
MA14
MA13
AVCC
MA12
AGND
QVCC
QGND
MA11
MA10
MA9
MA8
AGND
MA7
AVCC
MA6
MA5
MA4
AGND
MA3
MA2
MA1
MA0
SCK/SCL
EXTAL
QVCC
QGND
PINIT
PGND
PCAP
PVCC
SGND
MISO/SDA
RESET
MODA/IRQA
MODB/IRQB
MODC/NMI
SVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
–
O
O
O
O
–
O
–
–
–
O
O
O
O
–
O
–
O
O
O
–
O
O
O
O
I
I
–
–
I
–
I
–
–
I
I
I
I
I
–
Function
Pin No.
Pin Name
I/O
Address data output to S-RAM
Ground for address bus buffer
Address data output to S-RAM
Power supply for address bus buffer (+5V)
Address data output to S-RAM
Ground for address bus buffer
SPI serial clock signal input from system controller
External frequency input (3 MHz)
Power supply for internal logic (+5V)
Ground for internal logic
PLL initialize input (Fixed at “L”)
Ground for PLL
PLL filter input (Connected to 0.01
µ
F capacitor)
Power supply for PLL (+5V)
Ground for serial port
Master data signal input from system controller
Reset signal input from system controller
Mode select A (Fixed at “H”)
Mode select B (Fixed at “L”)
Mode select C (Fixed at “H”)
Power supply for serial port (+5V)
Address data output to S-RAM
• IC3412 DOLBY Surround Digital Signal Processor (SSP424023FJ88)
• Abbreviation
PLL: Phase Locked Loop
— 44 —
Function
Master data signal output to system controller
SPI slave select signal input from system controller
Host request signal input from system controller
Ground for serial port
Audio serial data 2 signal output
Audio serial data 1 signal output
Audio serial data 0 signal output
Power supply for serial port (+5V)
Serial clock transmission
Word select transmission
Serial clock reception
Ground for internal logic
Power supply for internal logic (+5V)
Ground for serial port
Word select reception
Audio serial data 1 signal input
Audio serial data 0 signal input
Debug serial signal output (Not used)
Debug serial signal input (Not used)
Debug serial clock signal input (Not used)
Debug request input (Fixed at “H”)
MOSI/HA0
SS/HA2
HREQ
SGND
SDO2
SDO1
SDO0
SVCC
SCKT
WST
SCKR
QGND
QVCC
SGND
WSR
SDI1
SDI0
DSO
DSI/OS0
DSCK/OS1
DR
MD7
MD6
MD5
MD4
DGND
MD3
MD2
MD1
DVCC
MD0
DGND
GPIO3
GPIO2
GPIO1
GPIO0
MRD
MWR
MA15/MCS1
MA16/MCS2/MCAS
O
I
I
–
O
O
O
–
O
O
I
–
–
–
I
I
I
O
I
I
I
I/O
I/O
I/O
I/O
–
I/O
I/O
I/O
–
I/O
–
I/O
I/O
I/O
O
O
O
O
O
Pin No.
Pin Name
I/O
Data input/output with S-RAM
Ground for data bus buffer
Data input/output with S-RAM
Power supply for data bus buffer (+5V)
Data input/output with S-RAM
Ground for data bus buffer
General DSP input/output (Not used)
General DSP output to system controller
Write strobe signal output to S-RAM
Read strobe signal output to S-RAM
Low address strobe signal output to S-RAM (Not used)
Column address strobe signal output to S-RAM
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Function
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