Sony STR-DB798 Service Manual ▷ View online
65
STR-DB798
Pin No.
Pin Name
I/O
Description
44
VSS
-
Ground terminal
45
NC
-
Not used
46
DAB_SEL
O
DAB selection signal output terminal Not used
47
RDS.DATA
I
RDS serial data input from the tuner unit (AEP and UK models only)
48
TUNER ST
I
FM stereo detection signal input from the tuner unit
49
TUNER TUNED
I
Tuned detection signal input from the tuner unit
50
TUNER MUTE
O
Muting request control signal output to the tuner unit
51
NC
-
Not used
52 to 54
MD2 to MD0
-
Not used
55
RSTX
I
System reset signal input from the reset signal generator "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
56
VCC
-
Power supply terminal (+3.3V)
57
X1
O
System clock output terminal (16.5 MHz)
58
X0
I
System clock input terminal (16.5 MHz)
59
VSS
-
Ground terminal
60
STOP
I
AC off detection signal input terminal
61
RDS_ CLK
I
RDS interrupt clock signal input from the tuner unit (AEP and UK models only)
62
POWER.ON/OFF
I
Power key input terminal "L": power on
63
SIRCS
I
Sircs signal input terminal
64
NC
-
Not used
65
TUNER DO
I
Serial data input from the tuner unit
66
TUNER LATCH
O
Serial data latch pulse signal output to the tuner unit
67
DIR ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
68
VCC
-
Power supply terminal (+3.3V)
69, 70
OPT SEL2,
OPT SEL1
O
Digital input selection signal output terminal
71
XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
72
DATA0
I
Audio serial data input from the digital audio interface receiver
73
XMODE
O
System reset signal output to the digital audio interface receiver "L": reset
74
CKSEL1
O
Output clock selection signal output to the digital audio interface receiver
75
CLK
O
Clock signal output to the digital audio interface receiver
76
CE
O
Chip enable signal output to the digital audio interface receiver
77
VCC
-
Power supply terminal (+3.3V)
78
AUDY_DATA
O
Serial data output to the lip sync adjust
79
DI
O
Write data output to the digital audio interface receiver
80
DO
I
Read data input from the digital audio interface receiver
81
AUDY_CLK
O
Serial data transfer clock signal output to the lip sync adjust
82
LRCK SW
O
Signal selection signal output terminal "L": boot strap signal, "H": L/R sampling clock signal
83
NC
-
Not used
84
GP12
O
Write signal output to the audio digital signal processor
85
DSP_BST
O
Boot strap signal output to the audio digital signal processor
86
XRST
O
System reset signal output to the audio digital signal processor "L": reset
87
PM1
O
PLL initialize signal output to the audio digital signal processor
88
DSP GP9
I
Read ready signal input from the audio digital signal processor
89
DSP_HCS
O
Chip select signal output to the audio digital signal processor
90
DSP_HACN
I
Acknowledge signal input from the audio digital signal processor
91
ADC:RST
O
System reset signal output to the A/D converter "L": reset
92
DAC_RST
O
System reset signal output to the D/A converter "L": reset
66
STR-DB798
Pin No.
Pin Name
I/O
Description
93
DA1LAT
O
Serial data latch pulse signal output to the D/A converter
94
DACCLK
O
Serial data transfer clock signal output to the D/A converter
95
DAC_MDI
O
Serial data output to the D/A converter
96
NO_USE
-
Not used
97
VCC
-
Power supply terminal (+3.3V)
98
VSS
-
Ground terminal
99
UP CON SDA
O
Serial data output to the video sync separator
100
UP CON SCL
O
Serial data transfer clock signal output to the video sync separator
101
VSS
-
Ground terminal
102
HDOUT
I
Serial data input from the audio digital signal processor
103
HDIN
O
Serial data output to the audio digital signal processor
104
HCLK
O
Serial data transfer clock signal output to the audio digital signal processor
105
DAB_CLK
O
Serial data transfer clock signal output terminal Not used
106
DAB_OUT
O
Serial data output terminal Not used
107
DAB_IN
I
Serial data input terminal Not used
108
DA1DO
I
Serial data input from the D/A converter
109, 110
SOT1, SIN1
-
Not used
111
EEPROM SCL
O
Serial data transfer clock signal output to the EEPROM
112
EEPROM SDA
I/O
Two-way data bus with the EEPROM
113
FL STB
O
Strobe signal output to the fluorescent indicator tube driver
114 to 117
VIDEO_SW1 to
VIDEO_SW4
O
Video selection signal output terminal
118
PROTECTOR
I
Protect detection signal input from the protect circuit
119
LIMITER.OUT
O
Output voltage control signal output terminal
120
FUNCTION.SW.
LAT
O
Serial data latch pulse signal selection signal output terminal
"L": for electrical volume, "H": for function switch
"L": for electrical volume, "H": for function switch
121
ANALOG_
DIGITAL
O
Analog/digital selection signal output terminal "L": analog, "H": digital
122
VCC
-
Power supply terminal (+3.3V)
123 to 125
NC
-
Not used
126
DAVS
-
Power supply terminal (+3.3V) (for internal D/A converter)
127
DAVC
-
Ground terminal (for internal D/A converter)
128
AVCC
-
Power supply terminal (+3.3V) (for analog)
129
AVRH
I
Reference voltage (+3.3V) input terminal
130
AVRL
I
Reference voltage (0V) input terminal
131
AVSS
-
Ground terminal (for analog)
132, 133
AD1, AD2
I
Front panel key input terminal (A/D input)
134
LIMITTER.IN
I
Voltage limit detection signal input terminal
135
RDS_SIGNAL
I
RDS signal input from the tuner unit (AEP and UK models only)
136
AD5 (NC)
-
Not used
137
NC
-
Not used
138
VERSION
I
Destination setting terminal
139
NC
-
Not used
140
VCC2
-
Power supply terminal (+3.3V)
141
BACKUP
-
Not used
142
GND
-
Ground terminal
143
OPEN
-
Not used
144
VSS
-
Ground terminal
67
STR-DB798
A/V SYNC BOARD IC2010 CXD9722TQ (LIP SYNC ADJUST)
Pin No.
Pin Name
I/O
Description
1 to 5
D1 to D5
I/O
Two-way data bus with the SD-RAM
6
VDD
-
Power supply terminal (+3.3V)
7, 8
D6, D7
I/O
Two-way data bus with the SD-RAM
9
VSS
-
Ground terminal
10
WE
O
Write enable signal output to the SD-RAM
11
CAS
O
Column address strobe signal output to the SD-RAM
12
RAS
O
Row address strobe signal output to the SD-RAM
13
CS
O
Chip select signal output to the SD-RAM
14
CLK
O
Clock signal output to the SD-RAM
15
CKE
O
Clock enable signal output to the SD-RAM
16
VDD
-
Power supply terminal (+3.3V)
17 to 22
A11, A10, A0 to A3
O
Address signal output to the SD-RAM
23
VSS
-
Ground terminal
24 to 29
A9 to A4
O
Address signal output to the SD-RAM
30
VSS
-
Ground terminal
31
DRSO
O
Surround R-ch data output terminal Not used
32
DLSO
O
Surround L-ch data output terminal Not used
33
DEXRO
-
Not used
34
DLFEO
O
Sub woofer data output terminal Not used
35
DCO
O
Center data output terminal Not used
36
VDD
-
Power supply terminal (+3.3V)
37
DRO
O
Front R-ch data output terminal Not used
38
DLO
O
Front L-ch data output terminal Not used
39
VSS
-
Ground terminal
40
DMRO
O
Data output terminal for R-ch down mix Not used
41
DMLO
O
Data output terminal for L-ch down mix Not used
42
VSS
-
Ground terminal
43
VDD
-
Power supply terminal (+3.3V)
44
DLDRO
O
Surround back audio data output to the D/A converter
45
CSWO
O
Center and sub woofer audio data output to the D/A converter
46
SLSRO
O
Surround audio data output to the D/A converter
47
FLFRO
O
Front audio data output to the D/A converter
48
VSS
-
Ground terminal
49
SPDIFO
O
Digital audio data output terminal Not used
50
TEST1
I
Input terminal for the test
51
TRST
I
Reset signal input from terminal Not used
52
TMS
I
Mode selection signal input terminal Not used
53
TCK
I
Clock signal input terminal Not used
54
TDI
I
Serial data signal input terminal Not used
55
TDO
O
Serial data signal output terminal Not used
56
TEST2
I
Input terminal for the test
57
SPDIFI
I
Digital audio data input terminal Not used
58
VSS
-
Ground terminal
59
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the audio digital signal processor
60
BCKI
I
Bit clock signal (2.8224 MHz) input from the audio digital signal processor
61
VDD
-
Power supply terminal (+3.3V)
68
STR-DB798
Pin No.
Pin Name
I/O
Description
62
VSS
-
Ground terminal
63
DLDRI
I
Surround back audio data input from the audio digital signal processor
64
CSWI
I
Center and sub woofer audio data input from the audio digital signal processor
65
SLSRI
I
Surround audio data input from the audio digital signal processor
66
FLFRI
I
Front audio data input from the audio digital signal processor
67
TEST3
I
Input terminal for the test
68
CLK512
I
Master clock signal input from the audio digital signal processor
69
VSS
-
Ground terminal
70
XRST
I
Reset signal input terminal "L": reset
71
VDD
-
Power supply terminal (+3.3V)
72
SCLK
I
Serial clock signal input from the main system controller
73
XCS
I
Chip select signal input from the main system controller
74
SI
I
Serial data input from the main system controller
75
SO
O
Serial data output to the main system controller
76
DEXRI
-
Not used
77
DMLI
I
Data input terminal for L-ch down mix Not used
78
DMRI
I
Data input terminal for R-ch down mix Not used
79
VSS
-
Ground terminal
80
PHRI
I
Clock signal input terminal Not used
81
BCKAI
I
Bit clock signal (2.8224 MHz) input terminal Not used
82
DQM
-
Not used
83
DLI
I
Front L-ch data input terminal Not used
84
DRI
I
Front R-ch data input terminal Not used
85
DCI
I
Center data input terminal Not used
86
DLFEI
I
Sub woofer data input terminal Not used
87
DLSI
I
Surround L-ch data input terminal Not used
88
DRSI
I
Surround R-ch data input terminal Not used
89
VSS
-
Ground terminal
90 to 95
D15 to D10
I/O
Two-way data bus with the SD-RAM
96
VDD
-
Power supply terminal (+3.3V)
97, 98
D9, D8
I/O
Two-way data bus with the SD-RAM
99
GND
-
Ground terminal
100
D0
I/O
Two-way data bus with the SD-RAM
Click on the first or last page to see other STR-DB798 service manuals if exist.