Sony STR-DB795 Service Manual ▷ View online
62
STR-DB795
DIGITAL BOARD IC1101 LC89056W-E (DIGITAL AUDIO INTERFACE RECEIVER)
Pin No.
Pin Name
I/O
Description
1
DISEL
I
Selection signal input terminal of data input terminal Fixed at "L" in this set
2
DOUT
O
Digital data output to the external output terminal
3 to 5
DIN0 to DIN2
I
Digital data input from the external input terminal
6
D.GND
-
Ground terminal (for digital)
7
DVDD
-
Power supply terminal (+3.3V) (for digital)
8
R
I
Input terminal for VCO gain control
9
VIN
I
Input terminal for VCO free-run frequency setting
10
LPF
O
PLL loop filter setting terminal
11
AVDD
-
Power supply terminal (+3.3V) (for analog)
12
AGND
-
Ground terminal (for analog)
13
CKOUT
O
Audio clock signal output to the audio digital signal processor and D/A converter
14
BCK
O
Bit clock signal (2.8224 MHz) output to the audio digital signal processor and A/D converter
15
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the audio digital signal processor and A/D
converter
converter
16
DATAO
O
Audio serial data output to the audio digital signal processor and system controller
17
XSTATE
O
Source clock selection monitor output to the system controller
18
DGND
-
Ground terminal (for digital)
19
DVDD
-
Power supply terminal (+3.3V) (for digital)
20
XMCK
O
System clock signal (12.288 MHz) output to the A/D converter
21
XOUT
O
System clock output terminal (12.288 MHz)
22
XIN
I
System clock input terminal (12.288 MHz)
23
EMPHA
O
Channel status emphasis information output terminal Not used
24
AUDIO
O
Channel status bit 1 output to the audio digital signal processor
25
CSFLAG
O
Channel status head 40 bit renewal flag output terminal Not used
26 to 29
F0/P0/C0 to
F3/P3/C3
O
Output terminal of input frequency calculation result Not used
30
DVDD
-
Power supply terminal (+3.3V) (for digital)
31
DGND
-
Ground terminal (for digital)
32
AUTO
O
Not used
33
BPSYNC
O
Non-PCM burst preamble sync signal output terminal Not used
34
ERROR
O
PLL lock error signal and data error flag output to the audio digital signal processor and system
controller
controller
35
DO
O
Read data output to the system controller
36
DI
I
Write data input from the system controller
37
CE
I
Chip enable signal input from the system controller
38
CLK
I
Clock signal input from the system controller
39
XSEL
I
Selection signal input terminal of crystal oscillator frequency Fixed at "H" in this set
40, 41
MODE0, MODE1
I
Mode setting terminal Fixed at "L" in this set
42
DGND
-
Ground terminal (for digital)
43
DVDD
-
Power supply terminal (+3.3V) (for digital)
44, 45
DOSEL0, DOSEL1
I
Output data format selection signal input terminal Fixed at "L" in this set
46
CKSEL0
I
Output clock selection signal input terminal Fixed at "L" in this set
47
CKSEL1
I
Output clock selection signal input from the system controller
48
XMODE
I
System reset signal input from the system controller "L": reset
•
IC Pin Function Description
63
STR-DB795
DIGITAL BOARD IC1201 CXD9718BQ (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XRST
I
System reset signal input from the system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
FS2
I
Sampling frequency selection signal input terminal Not used
5
VDDI
-
Power supply terminal (+2.5V)
6
FS1
I
Sampling frequency selection signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+2.5V)
11
VSS
-
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal "L": internal clock, "H": external clock Fixed at "L" in this set
14
SCKOUT
O
Internal system clock output terminal Not used
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter and digital audio interface
receiver
receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the A/D converter and digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A converter
21
VSS
-
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 26
SDO1 to SDO4
O
Audio serial data output to the D/A converter
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter and digital audio interface
receiver
receiver
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter and digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
-
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
SDCLK
I
Write signal input from the system controller
38
CLKEN
O
SD-RAM chip enable output terminal Not used
39
RAS
O
Row address strobe signal output terminal Not used
40
VDDI
-
Power supply terminal (+2.5V)
41
VSS
-
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used
43
DQM/OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
-
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at "H" in this set
48
VSS
-
Ground terminal
64
STR-DB795
Pin No.
Pin Name
I/O
Description
49
WMD0
I
External memory wait mode setting terminal Fixed at "H" in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
-
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal "L": enhanced mode, "H": normal mode Fixed at "H" in this set
58
MOD0
I
Operation mode setting terminal "L": single chip mode, "H": can not use Fixed at "L" in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
-
Power supply terminal (+2.5V)
61
VSS
-
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal (44.1 kHz) input terminal
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
-
Power supply terminal (+2.5V)
71
VSS
-
Ground terminal
72 to 75
D15/GP7 to
D12/GP4
I/O
Two-way data bus with the S-RAM
76
VDDE
-
Power supply terminal (+3.3V)
77 to 80
D11/GP3 to
D8/GP0
I/O
Two-way data bus with the S-RAM
81
VSS
-
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
-
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
-
Power supply terminal (+2.5V)
101
VSS
-
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
-
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
-
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
117 to 119
VSS
-
Ground terminal
120
VDDI
-
Power supply terminal (+2.5V)
65
STR-DB795
DIGITAL BOARD IC1703 MB91154PFV-G-121-BNDE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
PW RY
O
Relay drive signal output terminal (for main power) "H": relay on
2
H/P RY
O
Relay drive signal output terminal (for headphone) "H": relay on
3
SP.A.RY
O
Relay drive signal output terminal (for front A speaker) "H": relay on
4
SP B RY
O
Relay drive signal output terminal (for front B speaker) "H": relay on
5
SURR.RY
O
Relay drive signal output terminal (for surround speaker) "H": relay on
6
CTR/SW RY
O
Relay drive signal output terminal (for sub woofer) "H": relay on
7
SB.RY
O
Relay drive signal output terminal (for center/surround back speaker) "H": relay on
8
SUB T
O
Relay drive signal output terminal (for standby power) "H": relay on
9
VSS
-
Ground terminal
10
FUNCTION.JOG
(2B)
I
Jog dial pulse input from the rotary encoder (B phase input) (for INPUT SELECTOR)
11
FUNCTION.JOG
(2A)
I
Jog dial pulse input from the rotary encoder (A phase input) (for INPUT SELECTOR)
12
VOL.JOG (1B)
I
Jog dial pulse input from the rotary encoder (B phase input) (for MASTER VOLUME)
13
VOL.JOG (1A)
I
Jog dial pulse input from the rotary encoder (A phase input) (for MASTER VOLUME)
14
FL CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube driver
15
FL DATA
O
Serial data output to the fluorescent indicator tube driver
16
+/-.JOG (4B)
I
Jog dial pulse input from the rotary encoder (B phase input) (for MENU)
17
+/-.JOG (4A)
I
Jog dial pulse input from the rotary encoder (A phase input) (for MENU)
18
+/-.JOG (3B)
I
Jog dial pulse input from the rotary encoder (B phase input) (for -/+)
19
+/-.JOG (3A)
I
Jog dial pulse input from the rotary encoder (A phase input) (for -/+)
20
SP SW
I
Speaker switch input terminal "L": speaker on
21
VOL IC/TUNER
DATA
O
Serial data output to the tuner unit, audio selector, video selector and electrical volume
22
VOL IC/TUNER
CLK
O
Serial data transfer clock signal output to the tuner unit, audio selector, video selector and
electrical volume
electrical volume
23
VOL LAT
O
Serial data latch pulse signal output to the audio selector, video selector and electrical volume
24, 25
NC
-
Not used
26
VSS
-
Ground terminal
27
VCC
-
Power supply terminal (+3.3V)
28
RESET UP
CONVERT
-
Not used
29 to 32
NC
-
Not used
33
TP1
-
Not used
34 to 37
NC
O
Not used
38 to 40
TP4 to TP6
O
Not used
41
HP DETECT
I
Headphone detection signal input terminal "H": headphone is connected
42
D.POWER
O
Digital section power on/off control signal output terminal "H": power on
43
V.POWER
O
Video section power on/off control signal output terminal "H": power on
44
VSS
-
Ground terminal
45, 46
NC
-
Not used
47
RDS.DATA
I
RDS serial data input from the tuner unit (AEP and UK models only)
48
TUNER ST
I
FM stereo detection signal input from the tuner unit
49
TUNER TUNED
I
Tuned detection signal input from the tuner unit
50
TUNER MUTE
O
Muting request control signal output to the tuner unit
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