Sony STR-DB1070 / STR-DB870 Service Manual ▷ View online
53
STR-DB870/DB1070
•
DIGITAL BOARD IC1501 CDX9617R (AUDIO DSP1)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the system controller (IC1703)
3
EXTIN
I
Master clock input terminal Not used (fixed at “L”)
4
FS2
I
Sampling frequency select signal input terminal Not used (fixed at “L”)
5
VDDI
—
Power supply terminal (+2.5V)
6
FS1
I
Sampling frequency select signal input terminal Not used (fixed at “L”)
7
PLOCK
O
Internal PLL lock signal output terminal Not used (open)
8
VSS
—
Ground terminal
9
MCLK1
I
Systen clock input terminal (13.5MHz)
10
VDDI
—
Power supply terminal (+2.5V)
11
VSS
—
Ground terminal
12
MCLK2
O
Systen clock output terminal (13.5MHz)
13
MS
I
Master/slave active select terminal “L”: internal clock, “H”: external clock
14
SCKOUT
O
Internal system clock output terminal Not used (open)
15
LRCKI1
I
L/R sampling clock signal input from the audio interface receiver (IC1408)
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the audio interface receiver (IC1408)
18
SDI1
I
Audio data input from the A/D converter (IC1503)
19
LRCKO
O
L/R sampling clock signal output to the audio DSP2 (IC1601)
20
BCKO
O
Bit clock signal output to the audio DSP2 (IC1601)
21
VSS
—
Ground terminal
22
KFSIO
I/O
Audio clock signal (384fs/256fs) in/out terminal
23 to 26
SDO1 to SDO4
O
Audio serial data output to the audio DSP2 (IC1601)
27
SPDIF
O
S/PDIF output terminal Not used (open)
28
LRCKI2
I
L/R sampling clock signal input from the audio interface receiver (IC1408)
29
BCKI2
I
Bit clock signal input from the audio interface receiver (IC1408)
30
SDI2
I
Audio serial data input from the audio interface receiver (IC1408)
31
VSS
—
Ground terminal
32
HACN
O
Host acknowledge signal output to the system controller (IC1703)
33
HDIN
I
Host serial data input from the system contrller (IC1703)
34
HCLK
I
Host clock signal input from the system contrller (IC1703)
35
HDOUT
O
Host serial data output to the system contrller (IC1703)
36
HCS
I
Host chip select input from the system contrller (IC1703)
37
SDCLK
O
SD-RAM clock output terminal Not used (open)
38
CLKEN
O
SD-RAM clock enable output terminal Not used (open)
39
RAS
O
Row address strobe signal output terminal Not used (open)
40
VDDI
—
Power supply terminal (+2.5V)
41
VSS
—
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used (open)
43
DQM/OE0
O
Mask data output terminal
44
CS0
O
Chip select isignal output to the S-RAM (IC1502)
45
WE0
O
Write enable signal output to the S-RAM (IC1502)
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal (fixed at “H”)
48
VSS
—
Ground terminal
54
STR-DB870/DB1070
Pin No.
Pin Name
I/O
Description
49
WMD0
I
External memory wait mode setting terminal (fixed at “H”)
50
PAGE2
O
External memory page select signal output terminal Not used (open)
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page select signal output terminal Not used (open)
54
BOOT
I
Boot mode control signal input terminal Not used (fixed at “L”)
55
BTACT
O
Boot mode display signal output terminal Not used (open)
56
BST
I
Boot strap signal input from the system contorller (IC1703)
57
MOD1
I
Mode select signal input terminal “L”: 384fs, “H”: 256fs
58
MOD0
I
Mode select signal input terminal “L”: single chip mode, “H”: can not use
59
EXLOCK
I
Error lock signal input from the digital audio interface receiver (IC1408)
60
VDDI
—
Power supply terminal (+2.5V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used (open)
64 to 66
A15 to A13
O
Address signal output to the S-RAM (IC1502)
67
GP10
I
Serial clock input from the audio DSP2 (IC1601)
68
GP9
O
Signal output to the system controller (IC1703)
69
GP8
I
Audio transfer signal output to the digital audio inteface receiver (IC1408)
70
VDDI
—
Power supply terminal (+2.5V)
71
VSS
—
Ground terminal
72 to 75 D15/GP7 to D12/GP4
I/O
Two-way data bus with the S-RAM (IC1502)
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11/GP3 to D8/GP0
I/O
Two-way data bus with the S-RAM (IC1502)
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM (IC1502)
86
TDO
O
Emulation data output terminal Not used (open)
87
TMS
I
Emulation data input start/end select terminal Not used (open)
88
XTRST
I
Emulation break signal input terminal Not used (open)
89
TCK
I
Emulation clock signal input terminal Not used (open)
90
TDI
I
Emulation data input terminal Not used (open)
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM (IC1502)
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM (IC1502)
100
VDDI
—
Power supply terminal (+2.5V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM (IC1502)
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM (IC1502)
109, 110
A2, A1
O
Address signal output to the S-RAM (IC1502)
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM (IC1502)
113
PM
I
PLL initialize signal input from the system controller (IC1703)
114
SDI3, SDI4
I
Audio serial data input data terminal Not used (open)
116
SYNC
I
Sync/unsync select signal input terminal “L”: sync (fixed at “H”)
117 to 119
VSS
—
Ground terminal
120
VDDI
—
Power supply terminal (+2.5V)
55
STR-DB870/DB1070
•
DIGITAL BOARD IC1601 CXD9616R (AUDIO DSP2)
Pin No.
Pin Name
I/O
Description
1
VDDI
—
Power supply terminal (+2.5V)
2
EXTIN
I
Not used (fixed at “L”)
3, 4
WMD1, WMD0
I
External memory wait mode setting terminal (fixed at “H”)
5
MOD1
I
Mode select signal input terminal “L”: 384fs, “H”: 256fs
6
MOD0
I
Mode select signal input terminal “L”: single chip mode, “H”: can not use
7
VSS
—
Ground terminal
8
XRST
I
Reset signal input from the system controller (IC1703)
9
VSS
—
Ground terminal
10
SCKOUT
O
Serial clock signal output to the D/A converter (IC1201, 1202)
11
VDDI (PLL)
—
Power supply terminal (+2.5V) (for PLL)
12
SYNC
I
Sync/unsync select signal input terminal “L”: sync
13 to 15
PAGE2 to PAGE0
O
External memory page select signal output terminal Not used (open)
16
PLOCK
O
Internal PLL lock signal output teminal Not used (open)
17
BTACK
I
Boot mode display signal output teminal Not used (open)
18
VDDE
—
Power supply terminal (+3.3V)
19
VSS
—
Ground terminal
20 to 22
D31 to D29
I/O
Two-way data bus with the S-RAM (IC1602)
23
A17
O
Address signal output terminal Not used (open)
24
VSS
—
Ground terminal
25
SDO3
O
Audio serial data output to the D/A converter (IC1201)
26
SDO4
O
Audio serial data output to the D/A converter (IC1202)
27, 28
SDI1, SDI2
I
Audio serial data input from the audio DSP1 (IC1501)
29
LRCKI1
I
L/R sampling clock signal input from the audio DSP1 (IC1501)
30
VSS
—
Ground terminal
31, 32
D28, D27
I/O
Two-way data bus with the S-RAM (IC1602)
33
A16
O
Address signal output terminal Not used (open)
34
A15
O
Address signal output to the S-RAM (IC1602)
35
SDI3
I
Audio serial date input from the audio DSP1 (IC1501)
36
L2
—
Not used (open)
37
VDDI
—
Power supply terminal (+2.5V)
38
BCKI1
I
Bit clock signal input from the audio DSP1 (IC1501)
39
SDI4
I
Audio serial data input from the audio DSP1 (IC1501)
40
MS
I
Master/slave active select terminal “L”: internal clock, “H”: external clock (fixed at “L”)
41, 42
A14, A13
O
Address signal output to the S-RAM (IC1602)
43, 44
D26, D25
I/O
Two-way data bus with the S-RAM (IC1602)
45
VSS
—
Ground terminal
46
BCKI2
I
Bit clock signal input terminal Not used (open)
47, 48
FS2, FS1
I
Sampling frequency select signal input terminal Not used (open)
49
SPDIF
I
S/PDIF output terminal Not used (open)
50
A12
O
Address signal output to the S-RAM (IC1602)
51 to 53
D24 to D22
I/O
Two-way data bus with the S-RAM (IC1602)
54
VDDE
—
Power supply terminal (+3.3V)
55
VSS
—
Ground terminal
56 to 58
D21 to D19
I/O
Two-way data bus with the S-RAM (IC1602)
59
A11
O
Address signal output to the S-RAM (IC1602)
56
STR-DB870/DB1070
Pin No.
Pin Name
I/O
Description
60, 61
SDO1, SDO2
O
Audio serial data output to the D/A converter (IC1201)
62
KFSIO
I/O
Audio clock signal (384fs/256fs) in/out terminal
63
LRCKO
O
L/R sampling clock signal output to the D/A converter (IC1201, 1202)
64
BCKO
O
Bit clock signal output to the D/A converter (IC1201, 1202)
65
VDDI
—
Power supply terminal (+2.5V)
66
VSS
—
Ground terminal
67, 68
D18, D17
I/O
Two-way data bus with the S-RAM (IC1602)
69, 70
A10, A9
O
Address signal output to the S-RAM (IC1602)
71
CAS
O
Column address strobe signal output terminal Not used (open)
72
RAS
O
Row address strobe signal output terminal Not used (open)
73
VDDI
—
Power supply terminal (+2.5V)
74
HDIN
I
Host serial data input from the system contrller (IC1703)
75
HCLK
I
Host clock signal input from the system contrller (IC1703)
76
HCS
I
Host chip select input from the system contrller (IC1703)
77, 78
A8, A7
O
Address signal output to the S-RAM (IC1602)
79
D16
I/O
Two-way data bus with the S-RAM (IC1602)
80
D15
I/O
Two-way data bus terminal Not used (open)
81
VSS
—
Ground terminal
82
HDOUT
O
Host serial data input from the system contrller (IC1703)
83
HACN
O
Host acknowledge signal output to the system controller (IC1703)
84
CSO
O
Chip select signal output to the S-RAM (IC1602)
85
WEO
O
Write enable signal output to the S-RAM (IC1602)
86
A6
O
Address signal output to the S-RAM (IC1602)
87 to 89
D14 to D12
I/O
Two-way data bus terminal Not used (open)
90
VDDE
—
Power supply terminal (+3.3V)
91
VSS
—
Ground terminal
92 to 94
D11 to D9
I/O
Two-way data bus terminal Not used (open)
95
A5
O
Address signal output to the S-RAM (IC1602)
96
VDDI
—
Power supply terminal (+2.5V)
97
TCK
I
Emulation clock signal input terminal Not used (open)
98
TDI
I
Emulation data input terminal Not used (open)
99
TDO
O
Emulation data input terminal Not used (open)
100
TMS
I
Emulation data input start/end select Not used (open)
101
XTRST
I
Emulation break signal input terminal Not used (open)
102
VSS
—
Ground terminal
103, 104
D8, D7
I/O
Two-way data bus terminal Not used (open)
105, 106
A4, A3
O
Address signal output to the S-RAM (IC1602)
107, 108
GP10, GP9
—
Not used (open)
109
VDDI
—
Power supply terminal (+2.5V)
110
GP8
—
Not used (open)
111
GP7
I
Serial clock signal input terminal
112
GP6
—
Not used (open)
113, 114
A2, A1
O
Address signal output to the S-RAM (IC1602)
115, 116
D6, D5
I/O
Two-way data bus terminal Not used (open)
117
VSS
—
Ground terminal
118, 119
GP5, GP4
—
Not used (open)
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