Sony STR-DA90ESG Service Manual ▷ View online
– 17 –
Pin No.
Pin Name
I/O
Function
88
DOUT
O
Comparator output terminal
89
DOUTB
O
Comparator inverted output terminal
90
CSM
O
Clock (9.216 MHz) output terminal Not used (open)
91
GND
—
Ground terminal
92
WINGT
O
Test terminal Not used (open)
93
SYST0
O
Test terminal Not used (open)
94
SYST1
O
Test terminal Not used (open)
95
ADST0
O
Test terminal Not used (open)
96
ADST1
O
Test terminal Not used (open)
97
TMS
I
Test terminal Not used (fixed at “L”)
98
BUNR1
I
Test terminal Not used (fixed at “L”)
99
AGND
—
Ground terminal (for analog system)
100
AVDD
—
Power supply terminal (+5V) (for analog system)
– 18 –
DIGITAL BOARD IC3410 DSP56009FJ88F (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Function
1
AGND
—
Ground terminal (for address bus buffer)
2
MCS0
O
Chip select signal output to the external RAM device Not used (open)
3
MCS3
O
Chip select signal output to the external RAM device Not used (open)
4
MA14
O
Address signal output to the external RAM device Not used (open)
5
MA13
O
Address signal output to the external RAM device Not used (open)
6
AVCC
—
Power supply terminal (+5V) (for address bus buffer)
7
MA12
O
Address signal output to the external RAM device Not used (open)
8
AGND
—
Ground terminal (for address bus buffer)
9
QVCC
—
Power supply terminal (+5V) (for internal logic)
10
QGND
—
Ground terminal (for internal logic)
11
MA11
O
12
MA10
O
13
MA9
O
14
MA8
O
15
AGND
—
Ground terminal (for address bus buffer)
16
MA7
O
Address signal output to the external RAM device Not used (open)
17
AVCC
—
Power supply terminal (+5V) (for address bus buffer)
18
MA6
O
19
MA5
O
Address signal output to the external RAM device Not used (open)
20
MA4
O
21
AGND
—
Ground terminal (for address bus buffer)
22
MA3
O
23
MA2
O
24
MA1
O
25
MA0
O
26
SCK
I
Serial data reading clock signal input from the master controller (IC3413)
27
EXTAL
I
Master clock signal input terminal (3MHz)
28
QVCC
—
Power supply terminal (+5V) (for internal logic)
29
QGND
—
Ground terminal (for internal logic)
30
PINIT
I
Initialize input for the PLL circuit (fixed at “L”)
31
PGND
—
Ground terminal (for PLL circuit)
32
PCAP
I
Connected to the external capacitor for PLL circuit filter
33
PVCC
—
Power supply terminal (+5V) (for PLL circuit)
34
SGND
—
Ground terminal (for serial port)
35
MISO
I
Communication data input from the master controller (IC3413)
36
RESET
I
Reset signal input from the master controller (IC3413) “L”: reset
37
MODA
I
Mode selection terminal (fixed at “H”)
38
MODB
I
Mode selection terminal (fixed at “L”)
39
MODC
I
Mode selection terminal (fixed at “H”)
40
SVCC
—
Power supply terminal (+5V) (for serial port)
41
MOSI
O
Communication data output to the master controller (IC3413)
42
SS
I
SPI slave select signal input from the master controller (IC3413)
43
HREQ
I
Host request signal input from the master controller (IC3413)
44
SGND
—
Ground terminal (for serial port)
45
SDO2
O
Audio serial data output terminal Not used (open)
Address signal output to the external RAM device Not used (open)
Address signal output to the external RAM device Not used (open)
– 19 –
Pin No.
Pin Name
I/O
Function
46
SDO1
O
Audio serial data output to the digital signal processor (IC3412)
47
SDO0
O
Audio serial data output to the digital signal processor (IC3412)
48
SVCC
—
Power supply terminal (+5V) (for serial port)
49
SCKT
O
Audio serial data transfer clock signal output to the digital signal processor (IC3412)
50
WST
O
Word transmission output to the digital signal processor (IC3412)
51
SCKR
I
Bit clock signal (2.8224 MHz) input terminal
52
QGND
—
Ground terminal (for internal logic)
53
QVCC
—
Power supply terminal (+5V) (for internal logic)
54
SGND
—
Ground terminal (for serial port)
55
WSR
I
L/R sampling clock signal (44.1 kHz) input terminal
56
SDI1
I
Audio serial data input terminal
57
SDI0
I
Audio serial data input terminal
58
DSO
O
Debug serial data output terminal Not used (open)
59
DSI
I
Debug serial data input terminal Not used (open)
60
DSCK
I
Debug serial data reading clock signal input terminal Not used (open)
61
DR
I
Debug request signal input terminal Not used (fixed at “H”)
62
MD7
I/O
63
MD6
I/O
64
MD5
I/O
65
MD4
I/O
66
DGND
—
Ground terminal (for data bus buffer)
67
MD3
I/O
68
MD2
I/O
Two-way data bus with the external RAM device Not used (open)
69
MD1
I/O
70
DVCC
—
Power supply terminal (+5V) (for data bus buffer)
71
MD0
I/O
Two-way data bus with the external RAM device Not used (open)
72
DGND
—
Ground terminal (for data bus buffer)
73
GPIO3
I/O
74
GPIO2
I/O
75
GPIO1
I/O
76
GPIO0
I/O
77
MRD
O
Write strobe signal output to the external RAM device Not used (open)
78
MWR
O
Read strobe signal output to the external RAM device Not used (open)
79
MRAS
O
Row address strobe signal output to the external RAM device Not used (open)
80
MCAS
O
Column address strobe signal output to the external RAM device Not used (open)
Two-way data bus with the external RAM device Not used (open)
General digital signal processor in/out terminal Not used (open)
– 20 –
DIGITAL BOARD IC3412 SSP424023FJ88 (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Function
1
AGND
—
Ground terminal (for address bus buffer)
2
MCS0
O
Chip select signal output to the external RAM device Not used (open)
3
MA15
O
4
MA14
O
Address signal output to the S-RAM (IC3411)
5
MA13
O
6
AVCC
—
Power supply terminal (+5V) (for address bus buffer)
7
MA12
O
Address signal output to the S-RAM (IC3411)
8
AGND
—
Ground terminal (for address bus buffer)
9
QVCC
—
Power supply terminal (+5V) (for internal logic)
10
QGND
—
Ground terminal (for internal logic)
11
MA11
O
12
MA10
O
13
MA9
O
14
MA8
O
15
AGND
—
Ground terminal (for address bus buffer)
16
MA7
O
Address signal output to the S-RAM (IC3411)
17
AVCC
—
Power supply terminal (+5V) (for address bus buffer)
18
MA6
O
19
MA5
O
Address signal output to the S-RAM (IC3411)
20
MA4
O
21
AGND
—
Ground terminal (for address bus buffer)
22
MA3
O
23
MA2
O
24
MA1
O
25
MA0
O
26
SCK
I
Serial data reading clock signal input from the master controller (IC3413)
27
EXTAL
I
Master clock signal input terminal (3MHz)
28
QVCC
—
Power supply terminal (+5V) (for internal logic)
29
QGND
—
Ground terminal (for internal logic)
30
PINIT
I
Initialize input for the PLL circuit (fixed at “L”)
31
PGND
—
Ground terminal (for PLL circuit)
32
PCAP
I
Connected to the external capacitor for PLL circuit filter
33
PVCC
—
Power supply terminal (+5V) (for PLL circuit)
34
SGND
—
Ground terminal (for serial port)
35
MISO
I
Communication data input from the master controller (IC3413)
36
RESET
I
Reset signal input from the master controller (IC3413) “L”: reset
37
MODA
I
Mode selection terminal (fixed at “H”)
38
MODB
I
Mode selection terminal (fixed at “L”)
39
MODC
I
Mode selection terminal (fixed at “H”)
40
SVCC
—
Power supply terminal (+5V) (for serial port)
41
MOSI
O
Communication data output to the master controller (IC3413)
42
SS
I
SPI slave select signal input from the master controller (IC3413)
43
HREQ
I
Host request signal input from the master controller (IC3413)
44
SGND
—
Ground terminal (for serial port)
45
SDO2
O
Audio serial data output terminal (for rear side speaker)
Address signal output to the S-RAM (IC3411)
Address signal output to the S-RAM (IC3411)
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