DOWNLOAD Sony STR-DA80ES / TA-V88ES / TA-VA80ES Service Manual ↓ Size: 890.89 KB | Pages: 53 in PDF or view online for FREE

Model
STR-DA80ES TA-V88ES TA-VA80ES
Pages
53
Size
890.89 KB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
str-da80es-ta-v88es-ta-va80es.pdf
Date
PREV: Sony SEN-471 Service Manual

Sony STR-DA80ES / TA-V88ES / TA-VA80ES Service Manual ▷ View online

– 13 –
Pin No.
Pin Name
I/O
Function
46
D5
I/O
47
D4
I/O
48
D3
I/O
49
D2
I/O
50
D1
I/O
51
D0
I/O
52
VDD
—
Power supply terminal (+5V)
53
GND
—
Ground terminal
54
TI1
I
Test terminal    Not used (fixed at “H”)
55
VIN
I
VCXO input terminal (18.432 MHz)
56
VOUT
O
VCXO output terminal (18.432 MHz)
57
TI2
I
Test terminal    Not used (fixed at “L”)
58
TI3
I
Test terminal    Not used (fixed at “L”)
59
TLD8
I
Test terminal    Not used (fixed at “L”)
60
TCK
I
Test terminal    Not used (fixed at “L”)
61
TRP
O
Test terminal    Not used (open)
62
TD0
O
Test terminal    Not used (open)
63
PD0
O
Internal phase comparator output terminal
64
TI4
I
Test terminal    Not used (fixed at “L”)
65
PDD15
I
PDO out control signal input terminal    “L”: on
66
MUT0
O
Mute control signal output terminal    “H”: mute on
67
TI5
I
Test terminal    Not used (fixed at “L”)
68
VLDY
O
Test terminal    Not used (open)
69
DASYO
O
Test terminal    Not used (open)
70
DAOUT
O
Digital out signal output terminal (serial data stream output)
71
DAIN
I
Digital external input terminal    Through out to DAOUT (pin &º) when DASEL (pin &™)is “H”
Not used (open)
72
DASEL
I
Digital out selection terminal    Fixed at “L”
73
TI8
I
Test terminal    Not used (fixed at “L”)
74
C2F1
O
C2 error correction state monitor output terminal    Outputs if corrected properly
Not used (open)
75
C2F0
O
C2 error correction state monitor output terminal    Outputs number of errors at C2
Not used (open)
76
C1F1
O
C1 error correction state monitor output terminal    Outputs whether error is present at C1
Not used (open)
77
C1F0
O
C1 error correction state monitor output terminal    Outputs number of errors at C1
Not used (open)
78
MUT1
I
Mute signal input terminal    “H”: mute
79
VDD
—
Power supply terminal (+5V)
80
GND
—
Ground terminal
81
AVDD
—
Power supply terminal (+5V) (for analog system)
82
CPIN
I
Comparator input (+) terminal
83
CMIN
I
Comparator input (–) terminal
84
AGND
—
Ground terminal (for analog system)
85
TM4
I
Test terminal    Not used (fixed at “L”)
86
VDD
—
Power supply terminal (+5V)
87
DIN
I
Test terminal    Not used (fixed at “L”)
Two-way data bus with the S-RAM (IC3309)
– 14 –
Pin No.
Pin Name
I/O
Function
88
DOUT
O
Comparator output terminal
89
DOUTB
O
Comparator inverted output terminal
90
CSM
O
Clock (9.216 MHz) output terminal    Not used (open)
91
GND
—
Ground terminal
92
WINGT
O
Test terminal    Not used (open)
93
SYST0
O
Test terminal    Not used (open)
94
SYST1
O
Test terminal    Not used (open)
95
ADST0
O
Test terminal    Not used (open)
96
ADST1
O
Test terminal    Not used (open)
97
TMS
I
Test terminal    Not used (fixed at “L”)
98
BUNR1
I
Test terminal    Not used (fixed at “L”)
99
AGND
—
Ground terminal (for analog system)
100
AVDD
—
Power supply terminal (+5V) (for analog system)
– 15 –
   DIGITAL BOARD  IC3410  DSP56009FJ88F (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Function
1
AGND
—
Ground terminal (for address bus buffer)
2
MCS0
O
Chip select signal output to the external RAM device    Not used (open)
3
MCS3
O
Chip select signal output to the external RAM device    Not used (open)
4
MA14
O
Address signal output to the external RAM device    Not used (open)
5
MA13
O
Address signal output to the external RAM device    Not used (open)
6
AVCC
—
Power supply terminal (+5V) (for address bus buffer)
7
MA12
O
Address signal output to the external RAM device    Not used (open)
8
AGND
—
Ground terminal (for address bus buffer)
9
QVCC
—
Power supply terminal (+5V) (for internal logic)
10
QGND
—
Ground terminal (for internal logic)
11
MA11
O
12
MA10
O
13
MA9
O
14
MA8
O
15
AGND
—
Ground terminal (for address bus buffer)
16
MA7
O
Address signal output to the external RAM device    Not used (open)
17
AVCC
—
Power supply terminal (+5V) (for address bus buffer)
18
MA6
O
19
MA5
O
Address signal output to the external RAM device    Not used (open)
20
MA4
O
21
AGND
—
Ground terminal (for address bus buffer)
22
MA3
O
23
MA2
O
24
MA1
O
25
MA0
O
26
SCK
I
Serial data reading clock signal input from the master controller (IC3413)
27
EXTAL
I
Master clock signal input terminal (3MHz)
28
QVCC
—
Power supply terminal (+5V) (for internal logic)
29
QGND
—
Ground terminal (for internal logic)
30
PINIT
I
Initialize input for the PLL circuit (fixed at “L”)
31
PGND
—
Ground terminal (for PLL circuit)
32
PCAP
I
Connected to the external capacitor for PLL circuit filter
33
PVCC
—
Power supply terminal (+5V) (for PLL circuit)
34
SGND
—
Ground terminal (for serial port)
35
MISO
I
Communication data input from the master controller (IC3413)
36
RESET
I
Reset signal input from the master controller (IC3413)    “L”: reset
37
MODA
I
Mode selection terminal (fixed at “H”)
38
MODB
I
Mode selection terminal (fixed at “L”)
39
MODC
I
Mode selection terminal (fixed at “H”)
40
SVCC
—
Power supply terminal (+5V) (for serial port)
41
MOSI
O
Communication data output to the master controller (IC3413)
42
SS
I
SPI slave select signal input from the master controller (IC3413)
43
HREQ
I
Host request signal input from the master controller (IC3413)
44
SGND
—
Ground terminal (for serial port)
45
SDO2
O
Audio serial data output terminal    Not used (open)
Address signal output to the external RAM device    Not used (open)
Address signal output to the external RAM device    Not used (open)
– 16 –
Pin No.
Pin Name
I/O
Function
46
SDO1
O
Audio serial data output to the digital signal processor (IC3412)
47
SDO0
O
Audio serial data output to the digital signal processor (IC3412)
48
SVCC
—
Power supply terminal (+5V) (for serial port)
49
SCKT
O
Audio serial data transfer clock signal output to the digital signal processor (IC3412)
50
WST
O
Word transmission output to the digital signal processor (IC3412)
51
SCKR
I
Bit clock signal (2.8224 MHz) input terminal
52
QGND
—
Ground terminal (for internal logic)
53
QVCC
—
Power supply terminal (+5V) (for internal logic)
54
SGND
—
Ground terminal (for serial port)
55
WSR
I
L/R sampling clock signal (44.1 kHz) input terminal
56
SDI1
I
Audio serial data input terminal
57
SDI0
I
Audio serial data input terminal
58
DSO
O
Debug serial data output terminal    Not used (open)
59
DSI
I
Debug serial data input terminal    Not used (open)
60
DSCK
I
Debug serial data reading clock signal input terminal    Not used (open)
61
DR
I
Debug request signal input terminal    Not used (fixed at “H”)
62
MD7
I/O
63
MD6
I/O
64
MD5
I/O
65
MD4
I/O
66
DGND
—
Ground terminal (for data bus buffer)
67
MD3
I/O
68
MD2
I/O
Two-way data bus with the external RAM device    Not used (open)
69
MD1
I/O
70
DVCC
—
Power supply terminal (+5V) (for data bus buffer)
71
MD0
I/O
Two-way data bus with the external RAM device    Not used (open)
72
DGND
—
Ground terminal (for data bus buffer)
73
GPIO3
I/O
74
GPIO2
I/O
75
GPIO1
I/O
76
GPIO0
I/O
77
MRD
O
Write strobe signal output to the external RAM device    Not used (open)
78
MWR
O
Read strobe signal output to the external RAM device    Not used (open)
79
MRAS
O
Row address strobe signal output to the external RAM device    Not used (open)
80
MCAS
O
Column address strobe signal output to the external RAM device    Not used (open)
Two-way data bus with the external RAM device    Not used (open)
General digital signal processor in/out terminal    Not used (open)
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