Sony STR-DA5400ES Service Manual ▷ View online
STR-DA5400ES
125
COMMON 1
INH 2
VEE 3
GND 4
CH 0
7
VCC
8
A
5
LOGIC
LEVEL
LEVEL
CONVERTER
C
OUT
IN
CH 1
6
C
OUT
IN
1
G1#
2
A1
3
Y2
4
GND
7 G2#
8 VCC
6 Y1
5 A2
1
SYNC
SEP
V-SYNC
SEP
2 3
4 5
V IN
HD
VSS
VD
VDD
1
VCONT
2
VIN
3
GND
4
VOUT
5
FB
VREF
–
+
+
THERMAL &
OVER CURRENT
PROTECTION
ON/OFF
CONTROL
BIAS
6dB
AMP
7.5
Ω
DRIVER
1
13
BIAS
REF
6dB
AMP
7.5
Ω
DRIVER
5
9
2
12
4
10
6
8
7
VIN 1
VEE 1
VOUT 1
V+2
VEE 2
VIN 3
V+3
VEE 3
VOUT 3
POWER SAVE
GND
14 V+1
BIAS
6dB
AMP
7.5
Ω
DRIVER
3
11
VIN 2
VOUT 2
IC6006 NJM2581M-TE2
IC6008, 6009 LA7213
IC6011 TK73400AU3G0L-C
– CIS Board –
IC802 TC7W53F (TE12R)
– CONTROL Board –
IC2501 TC7WT125FU (TE12R)
1
7
8
3
4
4
5
2
6
1A
3Y
2A
GND
VCC
1Y
1Y
3A
2Y
IC2505, 2509 TC7W14FU (TE12R)
STR-DA5400ES
126
IN
1
SW
2
SS
5
ADJ
4
LATCH
&
DRIVER
ERROR AMP
COMPARATOR
OSCILLATOR
RESET
OVERCURRENT
PROTECTION
THERMAL
PROTECTION
REFERENCE
VOLTAGE
GND
3
ON/OFF
SOFT
START
PREG
+
+
+
–
–
IN
1
SW
2
SS
5
ADJ
4
LATCH
&
DRIVER
ERROR AMP
COMPARATOR
OSCILLATOR
RESET
OVERCURRENT
PROTECTION
THERMAL
PROTECTION
REFERENCE
VOLTAGE
GND
3
ON/OFF
SOFT
START
PREG
+
+
+
–
–
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
2G
2C3 2C2 2C1 2C0
2Y
VCC
2C3 2C2 2C1 2C0
STROBE
2G
OUTPUT
2Y
A
SELECT
DATA INPUTS
B
B
A
A
B
B
A
A
1G
1C3 1C2 1C1 1C0
1Y
STROBE
1G
B
SELECT
1C3 1C2 1C1 1C0 OUTPUT
1Y
GND
DATA INPUTS
1
OUT1
2
DC CUT1
3
IN1
4
MIC V+1
5
REG
6
NOISE
7
GND
14 OUT2
13 DC CUT2
12 IN2
11 MIC V+2
10 GV
9 STBY
8 V+
REG
GV
AMP1
AMP2
OVER
CURRENT
PROTECTOR
LATCH
&
DRIVER
OVER HEAT
PROTECTOR
REGULATOR
+
–
–
+
–
–
RESET
VREF
COMPARATOR
ERROR AMP
OSC
1
VIN
2
SW OUT
3
GND
4
VOS
5
S.S
IC2506, 2507 TC74VHC153FT (EL)
– DISPLAY Board –
IC703 NJM2173AV (TE2)
– DC-DC Board –
IC1401, 1404 SI-8050S-LF1101
IC1402, 1403 SI-8008HFEK
IC1405 SI-8120JF
– DCDC2 Board –
IC1451 SI-8008HFEK
IN
1
SW
2
SS
5
ADJ
4
LATCH
&
DRIVER
ERROR AMP
COMPARATOR
OSCILLATOR
RESET
OVERCURRENT
PROTECTION
THERMAL
PROTECTION
REFERENCE
VOLTAGE
GND
3
ON/OFF
SOFT
START
PREG
+
+
+
–
–
STR-DA5400ES
127
• IC Pin Function Description
DIGITAL BOARD IC2003 EP2C5T144C8N (FIELD PROGRAMMABLE GATE ARRAY)
Pin No.
Pin Name
I/O
Description
1
∗ASDO
O
AS data output to the fl ash memory
2
∗nCSO
O
Chip select signal output to the fl ash memory
3
MUTEOUT
O
Muting control signal output terminal
4
AMCKOUT
O
Audio master clock signal output to the D/A converter (foe audio section)
5
VCCIO1
-
Power supply terminal (+3.3V)
6
GND
-
Ground terminal
7
LRCKOUT
O
L/R sampling clock signal output for PCM audio signal to the lip sync adjust
8
-
-
Not used
9
BCKOUT
O
Bit clock signal output for PCM audio signal to the lip sync adjust
10
∗TDO
O
Data output terminal (for JTAG) Not used
11
∗TMS
I
Mode selection signal input terminal (for JTAG) Not used
12
∗TCK
I
Clock signal input terminal (for JTAG) Not used
13
∗TDI
I
Data input terminal (for JTAG) Not used
14
∗DATA0
I
Data input from the fl ash memory
15
∗DCLK
O
Clock signal output to the fl ash memory
16
∗nCE
I
Chip enable signal input terminal Not used
17
MCLKIN
I
Master clock signal input from the digital audio interface receiver or HDMI receiver
18
BCKIN
I
Bit clock signal input for PCM audio signal from the DSP2
19
GND
-
Ground terminal
20
∗nCONFIG
I
Confi guration control signal input terminal Not used
21
XRESET
I
Reset signal input from the system controller "L": reset
22
AMCKIN
I
Audio master clock signal input terminal
23
VCCIO1
-
Power supply terminal (+3.3V)
24
SD0OUT
O
PCM audio signal (front L/R) output to the lip sync adjust
25
SD1OUT
O
PCM audio signal (surround L/R) output to the lip sync adjust
26
-
-
Not used
27
SD2OUT
O
PCM audio signal (center, sub woofer) output to the lip sync adjust
28
SD3OUT
O
PCM audio signal (surround back L/R) output to the lip sync adjust
29
VCCIO1
-
Power supply terminal (+3.3V)
30
-
-
Not used
31
LRCKIN
I
L/R sampling clock signal input for PCM audio signal from the DSP2
32
-
-
Not used
33
GND
-
Ground terminal
34
GND_PLL1
-
Ground terminal (for PLL)
35
VCCD_PLL1
-
Power supply terminal (+1.2V) (digital system) (for PLL)
36
GND_PLL1
-
Ground terminal (for PLL)
37
VCCA_PLL1
-
Power supply terminal (+1.2V) (analog system) (for PLL)
38
GNDA_PLL1
-
Ground terminal (analog system) (for PLL)
39
GND
-
Ground terminal
40
SD0IN
I
PCM audio signal (front L/R) input from the DSP2
41
-
-
Not used
42
SD1IN
I
PCM audio signal (surround L/R) input from the DSP2
43
SD2IN
I
PCM audio signal (center, sub woofer) input from the DSP2
44
-
-
Not used
45
SD3IN
I
PCM audio signal (surround back L/R) input from the DSP2
46
VCCIO4
-
Power supply terminal (+3.3V)
47
I2CADRS0
-
Not used
48
I2CADRD1
-
Not used
49
GND
-
Ground terminal
50
VCCINT
-
Power supply terminal (+1.2V)
51
SDRAM
-
Not used
52, 53
-
-
Not used
54
VCCIO4
-
Power supply terminal (+3.3V)
STR-DA5400ES
128
Pin No.
Pin Name
I/O
Description
55
ERR
-
Not used
56
GND
-
Ground terminal
57
MIDDLE
O
Buffer status output to the system controller
58
EMPTY
O
Not used
59
FULL
O
Not used
60
-
-
Not used
61
GND
-
Ground terminal
62
VCCINT
-
Power supply terminal (+1.2V)
63
-
-
Not used
64
MODE
I
Not used
65
MUTE
I
Muting control signal input from the system controller
66
VCCIO4
-
Power supply terminal (+3.3V)
67
OUTPUTEN
I
Not used
68
GND
-
Ground terminal
69
MEMCLR
I
Not used
70
TXSTART
I
Not used
71
RXSTART
I
Not used
72
SDA
I/O
I2C data bus with the D/A converter (for audio section), system controller and video input
selector
selector
73
BA1
O
Bank address signal output terminal Not used
74
BA0
O
Bank address signal output to the SD-RAM
75
INIT_DONE
-
Not used
76
XCS
O
Chip select signal output to the SD-RAM
77
VCCIO3
-
Power supply terminal (+3.3V)
78
GND
-
Ground terminal
79
XRAS
O
Row address signal output to the SD-RAM
80
XCAS
O
Column address signal output to the SD-RAM
81
XWE
O
Write enable signal output to the SD-RAM
82
∗nSTATUS
-
Confi guration status terminal Not used
83
∗CONF_DONE
O
Confi guration status output terminal
84, 85
∗MSEL1, ∗MSEL0
I
Mode setting terminal
86
LDQM
O
Data mask signal output to the SD-RAM (lower byte)
87
-
-
Not used
88
SCL
I
I2C clock signal input from the system controller
89
-
-
Not used
90
SYSCLK
I
System clock signal input terminal
91
-
-
Not used
92 to 94
A0 to A2
O
Address signal output to the SD-RAM
95
VCCIO3
-
Power supply terminal (+3.3V)
96, 97
A3, A4
O
Address signal output to the SD-RAM
98
GND
-
Ground terminal
99 to 101
A5 to A7
O
Address signal output to the SD-RAM
102
VCCIO3
-
Power supply terminal (+3.3V)
103, 104
A8, A9
O
Address signal output to the SD-RAM
105
GND
-
Ground terminal
106
GND_PLL2
-
Ground terminal (for PLL)
107
VCCD_PLL2
-
Power supply terminal (+1.2V) (digital system) (for PLL)
108
GND_PLL2
-
Ground terminal (for PLL)
109
VCCA_PLL2
-
Power supply terminal (+1.2V) (analog system) (for PLL)
110
GNDA_PLL2
-
Ground terminal (analog system) (for PLL)
111
GND
-
Ground terminal
112
A10
O
Address signal output to the SD-RAM
113
A11
O
Address signal output terminal Not used
114, 115
D0, D1
I/O
Two-way data bus with the SD-RAM
116
VCCIO2
-
Power supply terminal (+3.3V)
117
GND
-
Ground terminal
