Sony STR-DA333ES / STR-DA555ES Service Manual ▷ View online
– 67 –
Description
Front speaker A relay
Front speaker B relay
Center speaker relay
Rear speaker relay
Sub woofer relay
Headphones relay
Power relay
Direct/pass relay
Digital input select 2 (SN74HC151)
Digital input select 1 (SN74HC151)
Digital input select 0 (SN74HC151)
Test port 0 (Not connected, open)
Front gain control 4
Front gain control 8
Front gain control 16
Center gain control 3
Center gain control 6
Center gain control 12
Ground
Woofer gain control 3
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pin Name
RY-FRONT/A
RY-FRONT/B
RY-CENTER
RY-REAR
WOOFER-RY
RY-HP
RY-POWER
RY-DIRECT-PASS
DIG-IN2
DIG-IN1
DIG-IN0
TEST0
FRONT4
FROUT8
FRONT16
C3
C6
C12
VSS
SW3
I/O
O
O
O
O
O
O
O
O
I
I
I
—
O
O
O
O
O
O
—
O
– 68 –
I/O
O
O
I
O
I
—
O
I
I
I
I
—
—
—
I
—
I
O
—
O
O
O
I
—
—
I
O
O
O
O
—
O
O
O
O
O
O
O
O
I
I
I
—
I
I
I
I
—
Description
EIAJ data and parity flag output terminal
Emphasis monitor output terminal ("H" = ON)
RC oscillator input terminal
RC oscillator output terminal
Microprocessor I/F select input terminal (CCB: H, SUB: L) (Connected to ground)
Digital ground
Clock output select terminal ("L" = 256 fs, "H" = 128 fs) (Connected to ground)
Clock input select terminal ("H" = 512 fs, "L" = 384 fs)
Test terminal (Connected to ground)
Test terminal (Connected to ground)
Reset input terminal
Digital power supply 0.5 V
Not used (Not connected, open)
Analog power supply +5 V
VCO oscillation band adjustment input terminal
Analog ground
VCO free-running frequency setting input terminal
External LPF is connected to this terminal for PLL
Digital power supply +5 V
CD subcode I/F and block sync output terminal
CD subcode I/F and data output terminal
CD subcode I/F and frame sync output terminal
CD subcode I/F and shift clock input terminal for data reading
Digital ground
Digital power supply +5 V
Crystal oscillator input terminal
Crystal oscillator output terminal
VCO and crystal oscillator clock output terminal
256fs or 128fs clock output terminal (Selected by CLKMD terminal)
Error mute output terminal
Digital ground
Sampling frequency monitor output terminal
Sampling frequency monitor output terminal
Bit clock output terminal
Audio data output terminal
L, R clock output terminal (L-ch: H, R-ch: L)
Microprocessor I/F and subcode Q data sync output terminal
Microprocessor I/F. When CCB/SUB is L, data output terminal (3-state output)
Microprocessor I/F. When CCB/SUB is H, data output terminal (high level open drain output) (Not connected)
Microprocessor I/F. Data input terminal
Microprocessor I/F. Chip enable/latch input terminal
Microprocessor I/F. Clock input terminal
Digital power supply +5 V
Built-in amplifier data input terminal (Connected to ground)
Built-in amplifier data input terminal (Connected to ground)
Built-in amplifier data input terminal (Connected to ground)
Built-in amplifier data input terminal
Digital ground
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
IC1101
CXD8495AQ (DIGITAL BOARD)
Pin Name
DOUT/V
EMPHA
RC1
RC2
CCB/SUB
D. GND
128/256
384/512
TEST
TEST
RESET
D. +5V
—
A. +5V
R
A. GND
VCO IN
VCO
D. +5V
SBSY
PW
SFSY
SB CLK
D. GND
D. +5V
XIN
XOUT
CLK OUT
CLK OUT
ERROR
D. GND
SUB1
SUB2
BCK
DATA OUT
LRCK
LD/DQSY
SRDT
DO
DI/SWDT
CE/XLAT
CL/SCLK
D. +5V
DIN1
DIN2
DIN3
DIN4
D. GND
– 69 –
I/O
—
O
I
—
I
I
—
—
O
I
I
I/O
—
—
I/O
I
—
—
I/O
—
—
I/O
—
—
—
I/O
—
I/O
O
—
—
O
O
O
I/O
—
—
I/O
O
—
O
O
I
I
O
I
O
Description
Ground
Serial data output
Conditional jump input terminal (7 pin: Connected to ground)
Not used (Connected to ground)
HCIF data write
HCIF data read
Ground
Power supply +3.3 V
HCIF ready signal. Open drain
HCIF chip select
HCIF address input
HCIF data input/output
Ground
Power supply +3.3 V
HCIF data input/output
Reset input "L": active
Test data output. Not used. (Not connected)
Ground
External RAM data input/output
Ground
Power supply +3.3 V
External RAM data input/output
Test data input. Not used. (Connected to ground)
Ground
Power supply +3.3 V
External RAM data input/output
Ground
External RAM data input/output
External RAM output cable
Ground
Power supply +3.3 V
External RAM column address strobe Not used. (Not connected)
External RAM write enable
External RAM raw address strobe. Not used. (Not connected)
External RAM address output/test data input
Ground
Power supply +3.3 V
External RAM data input/output
External RAM address output
Ground
External RAM address output
Not used
Test data input "L" = normal "H" = test (Connected to ground)
PLL input frequency select "L" = 256fs "H" = 128 fs (Connected to ground)
PLL output frequency select "L" = 768 fs "H" = 1024 fs (Connected to ground)
Master clock input
Master clock output (Not connected)
Pin No.
1
2 - 5
6,7
8
9
10
11
12
13
14
15
16 -20
21
22
23 - 25
26
27 -30
31
32 - 40
41
42
43 -49
50
51
52
53 -60
61
62 -69
70
71
72
73
74
75
76 -80
81
82
83 -89
90
91
92 -94
95
96
97
98
99
100
IC1112
CXD2712R (DIGITAL BOARD)
Pin Name
VSS3
SOA - SOD
ECJ0, ECJ1
—
XHDWR
XHDRD
VSS4
VDD2
HRDY
XHDCS
HA0
HD0 - HD4
VSS5
VDD3
HD5 - HD7
XRST
—
VSS6
SD0 - SD8
VSS7
VDD4
ED9 - ED15
—
VSS8
VDD5
ED16 - ED23
VSS9
ED24 - ED31
XOE
VSS10
VDD6
CAS
XWE
RAS
EA0 - EA4
VSS11
VDD7
EA5 - EA11
EA12
VSS0
EA13 - EA15
EA16
TSTA
PLDIVF
PLDIVB
CLK1
CLKO
– 70 –
I/O
—
—
—
—
I/O
I
I
I
O
O
—
—
I
I
I
I
I
Description
Ground
Power supply +3.3 V
Ground for PLL cell
VDD for PLL cell
PLL output/test clock input (Not connected)
PLL cell oscillation enable "L" oscillation enable "H" oscillation stop (Connected to ground)
Test data input "L" = normal "H" = test (Connected to ground)
Frequency counter input (Connected to ground)
LRCK0 divider output
BCK0 divider output
Ground
Power supply +3.3 V
BCK input
BCK input
LRCK input
LRCK input
Serial data input
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117 -120
Pin Name
VSS1
VDD0
AVSS
AVDD
PLLCK
XPLLEN
TST
LRCT
LROUT
BKOUT
VSS2
VDD1
BCK0
BCK1
LRCK0
LRCK1
SIA - SID
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