Sony STR-DA3100ES Service Manual ▷ View online
85
STR-DA3100ES
DIGITAL BOARD IC2601 MB91F155A-5ES-X101 (MAIN SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DSP HCLK
O
Serial data transfer clock signal output to the DSP1
2
DSP HDIN
O
Serial data output to the DSP1
3
1BST SEL
O
Signal selection signal output terminal “L”: boot strap signal, “H”: L/R sampling
clock signal
4
1XRST
O
System reset signal output to the DSP1 “L”: reset
5
1PM
O
PLL initialize signal output to the DSP1
6
1GP9
I
Read ready signal input from the DSP1
7
1BST
O
Boot strap signal output to the DSP1
8
1HCS
O
Chip select signal output to the DSP1
9
VSS
–
Ground terminal
10
1HDOUT
I
Serial data input from the DSP1
11
1HACN
I
Acknowledge signal input from the DSP1
12
2XRST
O
System reset signal output to the DSP2 “L”: reset
13
2PM
O
PLL initialize signal output to the DSP2
14
2GP3
I
Error signal input from the DSP2
15
2BST
O
Boot strap signal output to the DSP2
16
2HCS
O
Chip select signal output to the DSP2
17
2HDOUT
I
Serial data input from the DSP2
18
2HACN
I
Acknowledge signal input from the DSP2
19
2EXLOCK
O
Lock signal output to the DSP2
20
DIR-XMODE
O
System reset signal output to the digital audio interface receiver
21
DIR-CKSEL
O
Clock selection signal output to the digital audio interface receiver
22
NC
–
Not used
23
DIR-CE
O
Chip enable signal output to the digital audio interface receiver
24
DIR-DO
I
Read data input from the digital audio interface receiver
25
DAC MUTE
O
System muting on/off control signal output terminal “H”: muting on
26
VSS
–
Ground terminal
27
VCC
–
Power supply terminal (+3.3V)
28
DIR-ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
29
DIR-DATAO
I
Audio serial data input terminal
30
DIR-XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
31
TA_XCS
O
Chip select signal output to the lip sync adjust
32
TA_SO
I
Serial data input from the lip sync adjust
33
TA_XRST
O
System reset signal output to the lip sync adjust
34
MAIN
O
Trigger out signal output terminal (for MAIN)
35
2ND
O
Trigger out signal output terminal (for 2ND)
36
3RD
O
Trigger out signal output terminal (for 3RD)
37
O595 LAT
O
Serial data latch pulse output to the data decoder
38
O595 OE
O
Output enable signal output to the data decoder
39
DCOM CLK
O
Serial data transfer clock signal output to the digital audio interface receiver, lip sync
adjust and D/A converter
40
DCOM DATA
O
Serial data output to the digital audio interface receiver, lip sync adjust and D/A
converter
41
COM CLK
O
Serial data transfer clock signal output to the input select, electrical volume, data
decoder and tuner unit
42
COM DATA
O
Serial data output to the input select, electrical volume, data decoder and tuner unit
43
V595OE
O
Output enable signal output to the data decoder
44
VSS
–
Ground terminal
45
V595LAT
O
Serial data latch pulse output to the data decoder
86
STR-DA3100ES
Pin No.
Pin Name
I/O
Description
46
FUNCLAT
O
Serial data latch pulse output to the input select and electrical volume
47
O595 CLK
O
Serial data transfer clock signal output to the data decoder
48
VOLLAT
O
Serial data latch pulse output to the electrical volume
49
NC
–
Not used
50
MBUS-STS0
I
M-BUS status input from the sub system controller
51
A1OUT
O
SIRCS signal output for the CONTROL A1II Not used
52
MD2
I
Model distination signal input from the sub system controller
53
MD1
I
Model distination signal input terminal Not used
54
MD0
I
Model distination signal input from the sub system controller
55
RSTX
I
System reset signal input terminal “L”: reset
56
VCC
–
Power supply terminal (+3.3V)
57
X1
O
Main system clock output terminal (16.5 MHz)
58
X0
I
Main system clock input terminal (16.5 MHz)
59
VSS
–
Ground terminal
60
A1IN
I
SIRCS signal input for the CONTROL A1II Not used
61
SIRCS IN
I
SIRCS signal input terminal
62
POWER SW
I
Power key input terminal
63
RDSCLK
–
Not used
64 to 67
MBUS-STS1
I
M-BUS status input from the sub system controller
to MBUS-STS4
68
VCC
–
Power supply terminal (+3.3V)
69
RST TRG
O
Reset signal output terminal
70
END FLAG
O
End flag output to the sub system controller
71
A1-LAT
O
Serial data latch pulse signal output to the sub system controller
72
TUN-LAT
O
Serial data latch pulse signal output to the tuner unit
73
TUNED
I
Tuned detection signal input from the tuner unit
74
STEREO
I
FM stereo detection signal input from the tuner unit
75
TUNDO
I
Serial data input from the tuner unit
76
STOP
I
AC off detection signal input terminal
77
VCC
–
Power supply terminal (+3.3V)
78
NC
–
Not used
79
POWER RY
O
Relay drive signal (for main power) output terminal “H”: relay on
80
PROTECTOR
I
Over load detection signal input terminal
81
O595 DATA
O
Serial data output to the data decoder
82
D.POWER
O
Digital sircuit power on/off control signal output terminal
83
V.POWER
O
Video sircuit power on/off control signal output terminal
84
DIRECT LED
O
LED drive signal output terminal (for DIRECT)
85
DCS LED
O
LED drive signal output terminal (for Digital Cinema Sound)
86
M CH DEC. LED
O
LED drive signal output terminal (for MULTI CHANNEL DECODING)
87
DIMMER LED
O
LED drive signal output terminal (for DIMMER)
88, 89
FUNCJOG1,
I
Jog dial pulse input from the rotary encoder (for INPUT SELECTOR)
FUNCJOG2
90, 91
VOLJOG1,
I
Jog dial pulse input from the rotary encoder (for MASTER VOLUME)
VOLJOG2
92, 93
BASSJOG1,
I
Jog dial pulse input from the rotary encoder (for BASS)
BASSJOG2
94
PG3L OSDLAT
O
Serial data latch pulse signal output to the OSD driver
95
PG4L FLLAT
O
Serial data latch pulse output to the fluorescent indicator tube
96
PG5L FLBLK
O
Clear signal output to the fluorescent indicator tube
97
VCC
–
Power supply terminal (+3.3V)
87
STR-DA3100ES
Pin No.
Pin Name
I/O
Description
98
VSS
–
Ground terminal
99
EEP SDA
I/O
Two-way data bus with the EEPROM
100
EEP SCL
O
Serial data transfer clock signal output to the EEPROM
101
VSS
–
Ground terminal
102
OSD-CLK
O
Serial data transfer clock signal output to the OSD driver
103
OSD-DAT
O
Serial data output to the OSD driver
104
RDS DATA
–
Not used
105, 106
TREBJOG1,
I
Jog dial pulse input from the rotary encoder (for TREBLE)
TREBJOG2
107
UPCOM DAT
I/O
Two-way data bus with the chroma decoder
108
UPCOM CLK
O
Serial data transfer clock signal output to the chroma decoder
109
SOT1
O
Serial data output to the RS-232C
110
SIN1
I
Serial data input from the RS-232C
111
FLCLK
O
Serial data transfer clock signal output to the fluorescent indicator tube
112
FLDATA
O
Serial data output to the fluorescent indicator tube
113
DAC LAT
O
Serial data latch pulse signal output to the D/A coverter
114
AD/AD RST
O
System reset signal output to the D/A coverter and A/D converter
115
DAC LAT
I
Serial data input from the D/A converter
116, 117
SP-A, SP-B
I
Front speaker selection switch input terminal
118, 119
MENU JOG1,
I
Jog dial pulse input from the rotary encoder (for MENU)
MENU JOG2
120, 121
MAIN MENU JOG1,
I
Jog dial pulse input from the rotary encoder (for MAIN MENU)
MAIN MENU JOG2
122
VCC
–
Power supply terminal (+3.3V)
123
SUB VOL LAT
O
Serial data latch pulse signal output terminal Not used
124
AC MUTE
O
Muting on/off control signal output terminal Not used
125
DATA FEINT
–
Not used
126
DAVS
–
Ground terminal (for D/A converter)
127
DAVC
–
Power supply terminal (+3.3V) (for D/A converter)
128
AVCC
–
Power supply terminal (+3.3V) (for A/D converter)
129
AVRH
–
Reference voltage (+3.3V) input terminal (for A/D converter)
130
AVRL
–
Reference voltage (0V) input terminal (for A/D converter)
131
AVSS
–
Ground terminal (for A/D converter)
132 to134
AD1 to AD3
I
Front panel key input terminal (A/D input)
135
VERSION
I
Destination setting terminal
136
RDSSIGNAL
–
Not used
137
HP-SW
I
Headphone detection signal input terminal “H”: headphone is connected
138, 139
+/–JOG1,
I
Jog dial pulse input from the rotary encoder (for –/+)
+/–JOG2
140
VCC2
–
Power supply terminal (+3.3V)
141
BACUP
–
Power supply terminal (+3.3V) (for back up)
142
X0A
I
Sub system clock input terminal Not used
143
X1A
O
Sub system clock output terminal Not used
144
VSS
–
Ground terminal
88
STR-DA3100ES
DIGITAL BOARD IC2701 TMP87C447U-1F23 (SUB SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
STAT0
O
M-BUS status output to the main system controller
2
CARRIER-OUT
O
SIRCS signal on/off control signal output terminal Not used
3
FLASH
I
Not used
4
MBUS
I
Not used
5
CTRL-LATCH
I
Serial data latch pulse signal input from the main system controller
6, 7
–
–
Not used
8
SIRSTS
O
Not used
9
–
–
Not used
10
SIRCS-INPUT
I
SIRCS signal input terminal
11
A1-OUT
O
SIRCS signal output for CONTROL A1II Not used
12
A1-IN
I
SIRCS signal input for CONTROL A1II Not used
13
GND
–
Ground terminal
14
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input,
then it changes to “H”
15
XIN
I
System clock input terminal (7.28 MHz)
16
XOUT
O
System clock output terminal (7.28 MHz)
17
GND
–
Ground terminal
18
VDD
–
Power supply terminal (+5V)
19
RESETC
O
Reset signal output to the main system controller
20
RESETN
O
Not used
21
OUTHI1
O
Not used
22
OUTLO1
O
Not used
23
OUTHI2
O
Model distination signal output to the main system controller
24
OUTLO2
O
Model distination signal output to the main system controller
25
ENDFLG
I
End flag input from the main system controller
26
UARTIN
I
Serial data input from the RS-232C
27 to 32
–
–
Not used
33
SIRCS-OUT
O
SIRCS signal output terminal Not used
34 to 36
–
–
Not used
37
MBUS_TV
I
Not used
38
MBUS_V2
I
Not used
39
MBUS_V1
I
Not used
40
VDD
–
Power supply terminal (+5V)
41 to 44
STAT4 to STAT1
O
M-BUS status output to the main system controller
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