Sony STR-DA2400ES / STR-DG920 Service Manual ▷ View online
STR-DA2400ES/DG920
89
Pin No.
Pin Name
I/O
Description
143
CVCC18
-
Power supply terminal (+1.8V)
144
Q11
O
Serial data output to the HDMI transceiver and video processor
STR-DA2400ES/DG920
90
DIGITAL VIDEO BOARD IC3508 SII9134CTU (HDMI TRANSCEIVER)
Pin No.
Pin Name
I/O
Description
1
DE
I
Data enable signal input from the HDMI receiver
2
HSYNC
I
Horizontal sync signal input from the HDMI receiver
3
VSYNC
I
Vertical sync signal input from the HDMI receiver
4
SPDIF
I
S/PDIF signal input from the HDMI receiver
5
MCLK
I
Master clock signal input from the HDMI receiver
6 to 9
SD3 to SD0
I
PCM audio signal input from the HDMI receiver
10
WS
I
L/R sampling clock signal input from the HDMI receiver
11
SCK
I
Bit clock signal input from the HDMI receiver
12
CVCC18
-
Power supply terminal (+1.8V)
13
GND
-
Ground terminal
14
IOVCC33
-
Power supply terminal (+3.3V)
15
DCLK
I
Not used
16
DR0
I
Not used
17
DL0
I
Not used
18
DR1
I
Not used
19
DL1
I
Not used
20
DR2
I
Not used
21
DL2
I
Not used
22
DR3
I
Not used
23
DL3
I
Not used
24
INT
O
Interrupt signal output to the HDMI controller
25
RESET#
I
Reset signal input from the HDMI controller "L": reset
26
AGND
-
Ground terminal
27
EXT_SWG
-
Not used
28
PVCC1
-
Power supply terminal (+1.8V)
29
AGND
-
Ground terminal
30
TXC-
O
TMDS clock (negative) output to the HDMI OUT connector
31
TXC+
O
TMDS clock (positive) output to the HDMI OUT connector
32
AVCC18
-
Power supply terminal (+1.8V)
33
TX0-
O
TMDS data (negative) output to the HDMI OUT connector
34
TX0+
O
TMDS data (positive) output to the HDMI OUT connector
35
AGND
-
Ground terminal
36
TX1-
O
TMDS data (negative) output to the HDMI OUT connector
37
TX1+
O
TMDS data (positive) output to the HDMI OUT connector
38
AVCC18
-
Power supply terminal (+1.8V)
39
TX2-
O
TMDS data (negative) output to the HDMI OUT connector
40
TX2+
O
TMDS data (positive) output to the HDMI OUT connector
41
AGND
-
Ground terminal
42
PVCC2
-
Power supply terminal (+1.8V)
43
AGND
-
Ground terminal
44
AVCC33
-
Power supply terminal (+3.3V)
45
DCCPWR5V
I
Power supply voltage (+5V) input terminal
46
DSCL
O
I2C clock signal output to the HDMI OUT connector
47
DSDA
I/O
I2C data bus with the HDMI OUT connector
48
CSCL
I
I2C clock signal input from the HDMI controller
49
CSDA
I/O
I2C data bus with the HDMI controller, EEPROM, and HDMI receiver
50
CI2CA
-
Not used
51
HPD
I
Hot plug detection signal input from the HDMI OUT connector
52
TMODE
-
Not used
53
IOVCC33
-
Power supply terminal (+3.3V)
54
GND
-
Ground terminal
55
VPP18
-
Power supply terminal (+1.8V)
56 to 63
D35 to D28
I
Serial data input from the HDMI receiver
64
CVCC18
-
Power supply terminal (+1.8V)
65
GND
-
Ground terminal
STR-DA2400ES/DG920
91
Pin No.
Pin Name
I/O
Description
66
IOVCC33
-
Power supply terminal (+3.3V)
67 to 75
D27 to D19
I
Serial data input from the HDMI receiver
76
CVCC18
-
Power supply terminal (+1.8V)
77 to 86
D18 to D9
I
Serial data input from the HDMI receiver
87
GND
-
Ground terminal
88
IDCK
I
Output data clock signal input from the HDMI receiver
89
IOVCC33
-
Power supply terminal (+3.3V)
90 to 98
D8 to D0
I
Serial data input from the HDMI receiver
99
CVCC18
-
Power supply terminal (+1.8V)
100
GND
-
Ground terminal
STR-DA2400ES/DG920
92
DIGITAL VIDEO BOARD IC3601 FLI8638-LF (VIDEO PROCESSOR)
Pin No.
Pin Name
I/O
Description
A1
NC
-
Not used
A2
MSTR1_SDA
O
Power detection signal output to the system controller
A3
MSTR1_SCL
O
Busy signal output to the system controller
A4, A5
FSDATA1, FSDATA3
I/O
Two-way data bus with the SD-RAM
A6
FSDQM0
O
Data mask signal output to the SD-RAM (upper byte)
A7 to A10
FSDATA5, FSDATA7,
FSDATA9, FSDATA11
I/O
Two-way data bus with the SD-RAM
A11
FSDQM1
O
Data mask signal output to the SD-RAM (lower byte)
A12, A13
FSDATA13,
FSDATA15
I/O
Two-way data bus with the SD-RAM
A14
VDDA18_DLL
-
Power supply terminal (+1.8V)
A15, A16
FSDATA17,
FSDATA19
I/O
Two-way data bus with the SD-RAM
A17
FSDQS2
O
Data strobe signal output to the SD-RAM (upper byte)
A18 to A21
FSDATA21, FSDATA23,
FSDATA25, FSDATA27
I/O
Two-way data bus with the SD-RAM
A22
FSDQS3
O
Data strobe signal output to the SD-RAM (lower byte)
A23, A24
FSDATA29, FSDATA31
I/O
Two-way data bus with the SD-RAM
A25, A26
RPLL_AGND
-
Ground terminal
B1
BDATA0
I
Digital video (blue) signal input terminal Not used
B2
OCM_UDO_1
O
UART communication transfer data output to the system controller
B3
OCM_UDI_1
I
UART communication transfer data input from the system controller
B4, B5
FSDATA0, FSDATA2
I/O
Two-way data bus with the SD-RAM
B6
FSDQS0
O
Data strobe signal output to the SD-RAM (upper byte)
B7 to B10
FSDATA4, FSDATA6,
FSDATA8, FSDATA10
I/O
Two-way data bus with the SD-RAM
B11
FSDQS1
O
Data strobe signal output to the SD-RAM (lower byte)
B12, B13
FSDATA12, FSDATA14
I/O
Two-way data bus with the SD-RAM
B14
VSSA18_DLL
-
Ground terminal
B15, B16
FSDATA16, FSDATA18
I/O
Two-way data bus with the SD-RAM
B17
FSDQM2
O
Data mask signal output to the SD-RAM (upper byte)
B18 to B21
FSDATA20, FSDATA22,
FSDATA24, FSDATA26
I/O
Two-way data bus with the SD-RAM
B22
FSDQM3
O
Data mask signal output to the SD-RAM (lower byte)
B23, B24
FSDATA28, FSDATA30
I/O
Two-way data bus with the SD-RAM
B25
RPLL_DGND
-
Ground terminal
B26
XTAL
O
System clock output terminal (19.6608 MHz)
C1 to C3
BDATA3 to BDATA1
I
Digital video (blue) signal input terminal Not used
C4
FSCKE
O
Clock enable signal output to the SD-RAM
C5
FSCLKN
O
Clock signal (negative) output to the SD-RAM
C6 to C8
FSADDR8 to FSADDR6
O
Address signal output to the SD-RAM
C9
FSVREF
O
Reference voltage output to the SD-RAM
C10 to
C18
FSADDR5, FSADDR12,
FSADDR9, FSADDR4,
FSADDR11, FSADDR3
to FSADDR0
O
Address signal output to the SD-RAM
C19
FSVREF
O
Reference voltage output to the SD-RAM
C20, C21 FSBKSEL1, FSBKSEL0
O
Bank select signal output to the SD-RAM
C22
FSCS1
O
Chip select signal output terminal Not used
C23
FSWE
O
Write enable signal output to the SD-RAM
C24
FSRAS
O
Row address strobe signal output to the SD-RAM
C25
RPLL_1.8V
-
Power supply terminal (+1.8V)
C26
TCLK
I
System clock input terminal (19.6608 MHz)
D1 to D3
BDATA6 to BDATA4
I
Digital video (blue) signal input terminal Not used
D4
DDR_2.5V
-
Power supply terminal (+2.5V)
D5
FSCLKP
O
Clock signal (positive) output to the SD-RAM
D6 to D8
DDR_2.5V
-
Power supply terminal (+2.5V)
D9
FSVREFVSS
-
Ground terminal
D10 to
D15
DDR_2.5V
-
Power supply terminal (+2.5V)
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