Sony STR-DA1800ES Service Manual ▷ View online
STR-DA1800ES
89
Pin No.
Pin Name
I/O
Description
69
OUT1_5VPWR
O
+5V power on/off control signal output terminal for HDMI OUT B (ZONE 2) connector
“H”: power on
“H”: power on
70 to 72
NC
O
Not used
73
ABT_RST
O
Reset signal output to the video deinterlacing “L”: reset
74
ABT_POWER_CNT
O
Power on/off control signal output terminal for video deinterlacing “H”: power on
75
SP_POWER_CNT
O
Power on/off control signal output terminal for HDMI section “H”: power on
76
H2_POWER_CNT
O
Power on/off control signal output terminal for video controller “H”: power on
77
NC
O
Not used
78
FLI_BUSY
O
Busy signal output to the video controller
79
HSYNC_SEL
O
Horizontal sync selection signal output terminal Not used
80
FLI_RESET
O
Reset signal output to the video controller “L”: reset
81 to 85
NC
O
Not used
86
SP_SDA
I/O
Two-way I2C data bus with the HDMI transceiver
87
NC
O
Not used
88
VSS
-
Ground terminal
89
VCC
-
Power supply terminal (+3.3V)
90
MU_SCL
I/O
Two-way I2C clock bus with the HDMI transceiver
91
S_RAM_CE
O
Chip enable signal output to the S-RAM
92
NC
O
Not used
93
S_RAM_OE
O
Output enable signal output to the S-RAM
94
S_RAM_WE
O
Write enable signal output to the S-RAM
95, 96
NC
O
Not used
97 to 102
TEST_1 to TEST_6
O
Test terminal
103
TEST_7
O
Boot selection signal output to the video controller
104
VSS
-
Ground terminal
105
VCC
-
Power supply terminal (+3.3V)
106 to
113
NC
O
Not used
114 to
121
S_RAM_D0 to
S_RAM_D7
I/O
Two-way data bus with the S-RAM
123 to
131
S_RAM_A1 to
S_RAM_A9
O
Address signal output to the S-RAM
132
VSS
-
Ground terminal
133
VCC
-
Power supply terminal (+3.3V)
134 to
138
S_RAM_A10 to
S_RAM_A14
O
Address signal output to the S-RAM
139
NC
O
Not used
140
BT_VUTX_BTRX
O
Serial data output to the BT board
141
BT_VURX_BTTX
I
Serial data input from the BT board
142
SP_RST
O
Reset signal output to the HDMI transceiver “L”: reset
143
SP_INT
I
Interrupt signal input from the HDMI transceiver
144
NW_M_RESET
O
Reset signal output to the network module “L”: reset
145
NW_ADC_RST
O
Reset signal output to the A/D converter “L”: reset
146
NW_SPI_REQ
I
Request signal input from the network module
147
NW_SPI_READY
I
Ready signal input from the network module
148
VSS
-
Ground terminal
149
VCC
-
Power supply terminal (+3.3V)
150
TEST_I2C_DATA
I/O
Two-way I2C data bus terminal Not used
151
NW_POWER
O
Not used
152
TEST_I2C_CLK
I/O
Two-way I2C clock bus terminal Not used
153
NW_SPI_CE
O
Chip enable signal output to the network module
154
NW_SPI_DOUT
O
Serial data output to the network module
155
NW_SPI_DIN
I
Serial data input from the network module
156
NW_SPI_CLK
O
Serial data transfer clock signal output to the network module
157
USB_MCHG
I
Music change signal input from the audio decoder
158
VUCTS_BTRTS
I
Clear to send signal input from the BT board
159
VURTS_BTCTS
O
Return to send signal output to the BT board
160
BT_RESET
O
Reset signal output to the BT board “L”: reset
161
BT_CNT
O
Power on/off control signal output terminal for Bluetooth section “H”: power on
162
FLI
I/O
Two-way I2C data bus with the video controller
STR-DA1800ES
90
Pin No.
Pin Name
I/O
Description
163
NC
O
Not used
164
FLI_SCL
I/O
Two-way I2C clock bus with the video controller
165
NC
O
Not used
166
USB_IP_SDA
I/O
Two-way I2C data bus with the EEPROM
167
NC
O
Not used
168
USB_IP_SCL
I/O
Two-way I2C clock bus with the EEPROM
169
MEM_SPI_CE
O
Chip enable signal output terminal Not used
170
MEM_SPI_DOUT
O
Serial data output terminal Not used
171
MEM_SPI_DIN
I
Serial data input terminal Not used
172
MEM_SPI_CLK
O
Serial data transfer clock signal output terminal Not used
173
MEM_PATH_SEL
O
Path selection signal output terminal Not used
174
USB_SDA
I/O
Two-way I2C data bus with the audio decoder
175
BT_Mute
I
Muting request signal input from the BT board
176
VCC
-
Power supply terminal (+3.3V)
STR-DA1800ES
91
Pin No.
Pin Name
I/O
Description
1
VDDA33_LBADC
-
Power supply terminal (+3.3V)
2 to 6
LBADC_IN1 to
LBADC_IN5
-
Not used
7
VSSA33_LBADC
-
Ground terminal
8
RESETn
I
Reset signal input from the video system controller “L”: reset
9
VBUFC_RPLL
-
Not used
10
VDD_RPLL_18
-
Power supply terminal (+1.8V)
11
GND_RPLL
-
Ground terminal
12
XTAL
O
System clock output terminal (19.6608 MHz)
13
TCLK
I
System clock input terminal (19.6608 MHz)
14
AVDD_RPLL_33
-
Power supply terminal (+3.3V)
15
VSYNC1_VGA
-
Not used
16
HSYNC1_VGA
-
Not used
17
STI_TM2
-
Not used
18
GPIO15/STI_TM1/
EXT_CSn
-
Not used
19
SCART16
-
Not used
20
CVDD_18
-
Power supply terminal (+3.3V)
21
CRVSS
-
Ground terminal
22
UART_DI
I
Update signal input terminal
23
UART_DO
O
Update signal output terminal
24
DDC_SCLK
-
Not used
25
DDC_SDATA
-
Not used
26
CVDD_18
-
Power supply terminal (+1.8V)
27
CRVSS
-
Ground terminal
28
MSTR_SCLK
O
Serial data transfer clock signal output to the EEPROM
29
MSTR_SDATA
I/O
Two-way serial data bus with the EEPROM
30
RVDD_33
-
Power supply terminal (+3.3V)
31
CRVSS
-
Ground terminal
32 to 35
GPIO0 to GPIO3
-
Not used
36
GPIO6/IRin
-
Not used
37
CVDD_18
-
Power supply terminal (+1.8V)
38
CRVSS
-
Ground terminal
39
GPIO7/IRQin
-
Not used
40
GPIO8/IRQout
-
Not used
41
SIPC_SCLK
I/O
Two-way I2C clock bus with the video system controller
42
SIPC_SDATA
I/O
Two-way I2C data bus with the video system controller
43
CVDD_18
-
Power supply terminal (+1.8V)
44
CRVSS
-
Ground terminal
45, 46
GPIO11/PWM0,
GPIO12/PWM1
-
Not used
47
RVDD_33
-
Power supply terminal (+3.3V)
48
CRVSS
-
Ground terminal
49
GPIO13/PWM2/
JTAG_RESET
-
Not used
50
GPIO14/PWM3/
SCART16_1
-
Not used
51
CVDD_18
-
Power supply terminal (+1.8V)
52
CRVSS
-
Ground terminal
53
GPIO4/VIDIN_HS
-
Not used
54
GPIO5/VIDIN_VS
-
Not used
55
VID2_CLK/ROM_OEn
-
Not used
56
VID_DE_FLD/A0/
GPIO16
-
Not used
57
I2S_SPDIF_IN_DATA
-
Not used
58
I2S_IN_WCLK/
GPIO50
-
Not used
59
I2S_IN_BCLK/
GPIO51
-
Not used
D-VIDEO NW BOARD IC3201 FLI30502AC (VIDEO CONTROLLER)
STR-DA1800ES
92
Pin No.
Pin Name
I/O
Description
60
I2S0_SPDIF_OUT_
DATA
-
Not used
61
I2S_OUT_WCLK/
GPIO52
-
Not used
62
I2S_OUT_BCLK/
GPIO53
-
Not used
63
I2S1_OUT_DATA
-
Not used
64
AUD_CLKOUT
-
Not used
65
CVDD_18
-
Power supply terminal (+1.8V)
66
CRVSS
-
Ground terminal
67
DEN
O
Data enable signal output to the video deinterlacing
68
DHS
O
Horizontal sync signal output to the video deinterlacing
69
DVS
O
Vertical sync signal output to the video deinterlacing
70
DCLK
O
Output data clock signal output to the video deinterlacing
71
PBIAS
-
Not used
72
PPWR
-
Not used
73
AVSS_LV
-
Ground terminal
74
AVDD_LV_33
-
Power supply terminal (+3.3V)
75 to 84
R0 to R7, G0, G1,
O
Digital video signal output to the video deinterlacing
85
AVSS_OUT_LV
-
Ground terminal
86
AVDD_OUT_LV_33
-
Power supply terminal (+3.3V)
87 to 96
G2 to G7, B0 to B3
O
Digital video signal output to the video deinterlacing
97
AVSS_OUT_LV
-
Ground terminal
98
AVDD_OUT_LV_33
-
Power supply terminal (+3.3V)
99 to 102
B4 to B7
O
Digital video signal output to the video deinterlacing
103
CVDD_18
-
Power supply terminal (+1.8V)
104
CRVSS
-
Ground terminal
105
GPIO49/A18
-
Not used
106
ROM_SCSn/
ROM_CSn
O
Chip select signal output to the serial fl ash
107
ROM_SCLK
O
Serial data transfer clock signal output to the serial fl ash
108
ROM_SDO
O
Serial data output to the serial fl ash
109
ROM_SDI
I
Serial data input from the serial fl ash
110
RVDD_33
-
Power supply terminal (+3.3V)
111
CRVSS
-
Ground terminal
112
EXT_ADC_CLAMP/
A15/OPM1
-
Not used
113
XOSD_CLK/A14/
OPM0
-
Not used
114
XOSD_HS/A13/FS1
-
Not used
115
XOSD_VS/A12/FS0
-
Not used
116
XOSD_FLD/A11/FT1
-
Not used
117
VBI_DATA_7/A10/FT0
-
Not used
118, 119
BT2, BT1
I
Boot selection signal input from the video system controller
120
VBI_DATA_4/A7/
GPO23/BT0
-
Not used
121
VBI_DATA_3/A6/
GPO22/OSC_SEL
-
Not used
122 to
124
VBI_DATA_2/A5/
GPIO21 to
VBI_DATA_0/A3/
GPIO19
-
Not used
125
VBI_VALID/A2/
GPIO18
-
Not used
126
VBI_CLK/A1/GPIO17
-
Not used
127
VID_DATA_IN_16/D0/
VID2_0
-
Not used
128
RVDD_33
-
Power supply terminal (+3.3V)
129
CRVSS
-
Ground terminal
130
VID_DATA_IN_17/D1/
VID2_1
-
Not used
131
CVDD_18
-
Power supply terminal (+1.8V)
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