Sony SRS-ZX1 Service Manual ▷ View online
SRS-ZX1
21
– AMP Board –
IC351 TPA3100D2PHPR
RINN 2
RINP 3
GND
AV
C
C
1
48
AV
C
C
47
SHUTDOWN
44
MUTE
45
FA
U
LT
46
VCLAMPL
30
GND
25
PVCCL
26
AGND 4
GND
GND
12
13
ROSC
14
VREG
15
AGND
17
GND
24
PVCCL
27
PGNDL
PGNDL
PGNDL
29
28
28
VBYP
16
–
+
+
+
–
–
+
+
+
–
GAIN
CONTROL
PWM
LOGIC
STARTUP
PROTECTION
LOGIC
BIASES
&
REFERENCE
VCCOK
VREGOK
THERMAL
SC DETECT
TLL INPUT
BUFFER
(VCC COMPLIANT)
TLL INPUT
BUFFER
(VCC COMPLIANT)
BSRP
43
ROUTP
41
+
–
–
+
–
–
LINP 5
LINN 6
+
–
–
–
+
+
–
–
–
+
GAIN
CONTROL
PWM
LOGIC
GATE
DRIVE
GAIN0 8
GAIN1 9
GAIN1 9
GAIN0 7
MSTR/SLV 10
SYNC 11
GAIN
CONTROL
TO GAIN
ADJUSTMENT
BLOCKS &
STARTUP LOGIC
RAMP
GENERATOR
GATE
DRIVE
+
–
–
+
–
–
8
AVCC
VREG
VBYP AVCC
VBYP
VBYP
VREG
AVCC
BSLP
18
LOUTP
19
LOUTP
20
VBYP
4V
REGULATOR
VCLAMP
GENERATOR
LOUTN
22
BSLN
23
LOUTN
21
GND
36
VCLAMPR
31
PGNDR
PGNDR
PGNDR
33
32
32
PVCCR
PVCCR
PVCCR
35
34
34
GATE
DRIVE
GATE
DRIVE
ROUTP
42
ROUTN
40
BSRN
38
GND
37
ROUTN
39
VCLAMP
GENERATOR
GAIN
GAIN
GAIN
GAIN
SRS-ZX1
22
• IC Pin Function Description
MAIN BOARD IC401 ADSP-21364KSWZ-1AA (DSP)
MAIN BOARD IC401 ADSP-21364KSWZ-1AA (DSP)
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V)
2, 3
CLKCFG0, CLKCFG1
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
fi xed at 6:1 in this set
fi xed at 6:1 in this set
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode selection signal input terminal fi xed at SPI master boot mode in this set
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V)
14
GND
-
Ground terminal
15
FLAG0
O
Chip select signal output to the fl ash ROM "L": active
DC/DC converter voltage control signal output terminal "H": +12V
DC/DC converter voltage control signal output terminal "H": +12V
16
FLAG1
I/O
Not used
17
AD7
I/O
Two-way address and data bus terminal Not used
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V)
24 to 26
AD6 to AD4
I/O
Two-way address and data bus terminal Not used
27
VDDINT
-
Power supply terminal (+1.2V)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way address and data bus terminal Not used
31
VDDEXT
-
Power supply terminal (+3.3V)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way address and data bus terminal Not used
35
WR
O
Write enable signal output terminal "L": active Not used
36, 37
VDDINT
-
Power supply terminal (+1.2V)
38
GND
-
Ground terminal
39
RD
O
Read enable signal output terminal "L": active Not used
40
ALE
O
Address latch enable signal output terminal Not used
41 to 43
AD15 to AD13
I/O
Two-way address and data bus terminal Not used
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V)
46
AD12
I/O
Two-way address and data bus terminal Not used
47
VDDINT
-
Power supply terminal (+1.2V)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way address and data bus terminal Not used
53
DAI_P1
I/O
Not used
54
VDDINT
-
Power supply terminal (+1.2V)
55
GND
-
Ground terminal
56
DSP_SO
I
Serial data input from the system controller
57
DSP_SI
O
Serial data output to the system controller
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V)
60
VDDINT
-
Power supply terminal (+1.2V)
61
GND
-
Ground terminal
62
DSP_SCK
I
Serial data transfer clock signal input from the system controller
63
AD_DATA
I
Audio data input from the A/D converter
64
MCLK
O
Master clock signal output to the A/D converter and D/A converter
65
AD_BCLK
I
Bit clock signal input from the A/D converter
66
VDDINT
-
Power supply terminal (+1.2V)
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V)
SRS-ZX1
23
Pin No.
Pin Name
I/O
Description
69
GND
-
Ground terminal
70
AD_LRCLK
I
L/R sampling clock signal input from the A/D converter
71
DAI_P9
I/O
Not used
72
VDDINT
-
Power supply terminal (+1.2V)
73
VDDEXT
-
Power supply terminal (+3.3V)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V)
76
GND
-
Ground terminal
77, 78
DAI_P10, DAI_P11
I/O
Not used
79
DA_DATA
O
Audio data output to the D/A converter
80
DA_BCLK
O
Bit clock signal output to the D/A converter
81
DA_LRCLK
O
L/R sampling clock signal output to the D/A converter
82
#DSP_CS
I
Chip select signal input from the system controller
83
VDDINT
-
Power supply terminal (+1.2V)
84, 85
GND
-
Ground terminal
86 to 89
DAI_P16 to DAI_P19
I/O
Not used
90
VDDINT
-
Power supply terminal (+1.2V)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V)
94
DAI_P20
I/O
Not used
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V)
97, 98
FLAG2, FLAG3
I/O
Not used
99
VDDINT
-
Power supply terminal (+1.2V)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V)
121
RESET
I
Reset signal input from the system controller "L": reset
122
SPIDS
I
SPI slave device selection signal input terminal "L": SPI slave device fi xed at "H"
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V)
125
SPICLK
O
Serial data transfer clock signal output to the fl ash ROM
126
MISO
I
Serial data input from the fl ash ROM
127
MOSI
O
Serial data output to the fl ash ROM
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V)
130
VDDEXT
-
Power supply terminal (+3.3V)
131
AVDD
-
Power supply terminal (+1.2V) (analog system)
132
GND
-
Ground terminal (analog system)
133
GND
-
Ground terminal
134
CLKOUT
O
Clock signal output terminal Not used
135
EMU
O
Emulation status signal output terminal (for JTAG)
136
TDO
O
Test data output terminal (for JTAG)
SRS-ZX1
24
Pin No.
Pin Name
I/O
Description
137
TDI
I
Test data input terminal (for JTAG)
138
TRST
I
Test reset signal input terminal (for JTAG) "L": reset
139
TCK
I
Test clock signal input terminal (for JTAG)
140
TMS
I
Test mode select signal input terminal (for JTAG)
141
GND
-
Ground terminal
142
CLKIN
I
Clock signal (24.576MHz) input terminal
143
XTAL
O
Crystal oscillator signal output terminal Not used
144
VDDEXT
-
Power supply terminal (+3.3V)
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