Sony SRF-M73 Service Manual ▷ View online
SRF-M73
– 13 –
– 14 –
– 15 –
– 16 –
• Waveforms
– KEY Board –
– KEY Board –
1
IC101
@¢
XOUT
200 mV/DIV, 10 µs/DIV
5-3.
SCHEMATIC DIAGRAM
•
See page 17 for IC Block Diagrams.
2
Q103 Base-1, Collector-2
(RADIO ON mode)
200 mV/DIV, 100 ns/DIV
(RADIO ON mode)
200 mV/DIV, 100 ns/DIV
3
Q103 Collector-1 (RADIO ON mode)
2 V/DIV, 100 ns/DIV
2 V/DIV, 100 ns/DIV
208 m Vp-p
13.3
µ
s
616 m Vp-p
243 ns
4.9 Vp-p
243 ns
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
specified.
•
¢
: internal component.
•
C
: panel designation.
•
U
: B+ Line.
•
H
: adjustment for repair.
• Power voltage is dc 3 V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
(
no mark : FM
(
) : AM
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
• Signal path.
F
: FM
f
: AM
FM FREE-RUN
– 17 –
• IC Block Diagrams
– MAIN Board –
– MAIN Board –
IC1
CXA1238M-T6
IC2
LA3550MTP-1
IC3
LA4533M
VCO
REGULATOR
FM FRONT-END
AM FRONT-END
MPX
REGULATOR
MONO/STEREO
SELECT
DECORD
AMP
MUTING
AUTO
BLEND
TUNING
INDICATOR
AM IF/
DET
FM IF/
DISCRI
RIPPLE
FILTER
BAND-PASS
MUTE
1
27
28
29
30
24
25
26
21
22
23
18
19
20
16
17
2
3
4
5
6
7
8
9
PLL LPF1
PILOT DET LPF2
PILOT DET LPF2
ST IND/VCO CHECK
L-CH OUT
VCC
R-CH OUT
RIPPLE FILTER
AGC AFC1
10
AGC AFC2
13
FM IF IN
14
AM IF IN
15
BAND SELECT
11
GND
12
TUNE IND
1/2
COUNTER
1/2
COUNTER
PD1
PD2
FM/AM FE OUT
FM GND
FM RF IN
AM RF IN
FM RF
REG
FM OSC
AFC
AM OSC
MUTE
FM DISCRI
GND
PLL LPF2
MPX REG
VCO
ON/OFF
1
2
3
4
5
6
7
8
9
10
14
13
12
11
OUT-1
OUT-2
DET IN
DET OUT
REF
VCC
GND
LP-OUT
LP-GAIN
LP-IN
HP-2
HP-1
IN-2
IN-1
POWER
SWITCH
MUTE
BIAS
AMP
AMP
1
2
3
4
5
6
7
8
9
10 MUTE
R-OUT
GND
L-OUT
VCC
PWR
R-IN
GND
L-IN
REG
– 18 –
5-4.
IC PIN FUNCTION DESCRIPTION
•
Pin No.
Pin Name
I/O
Description
1
IF ON
O
Power on/off control signal output for the AM IF amplifier circuit “L”: power on
“L” is output when AM scan mode
“L” is output when AM scan mode
2
POWER
O
Power on/off control signal output for the radio system power supply “H”: power on
3
BAND
O
FM/AM band selection signal output terminal “L”: AM, “H”: FM
4
PULSE POWER
O
Power on/off control signal output for the pulse meter circuit “H”: power on
Not used (open)
Not used (open)
5
MUTE
O
Muting on/off control signal output to the headphone amplifier (IC3) “L”: muting on
6 to 9
KS0 to KS3
O
Key scan signal output for the key matrix
10 to 13
KR0 to KR3
I
Key return signal input for the key matrix
14
CK
O
Serial clock signal output to the EEPROM (IC105)
15
DATA
I/O
Two-way data bus with the EEPROM (IC105)
16
CS
O
Chip select signal output to the EEPROM (IC105)
17
AM IF IN
I
AM intermediate frequency detect signal input terminal
18
GND
—
Ground terminal
19
EO
O
PLL error signal output terminal
20
VCOL
I
AM VCO input terminal
21
VCOH
I
FM VCO input terminal
22
VREG1
—
Power supply terminal (connected to the coupling capacitor)
23
VDD
—
Power supply terminal (+3V)
24
XOUT
O
System clock output terminal (75 kHz)
25
XIN
I
System clock input terminal (75 kHz)
26
VREG2
—
Power supply terminal (connected to the coupling capacitor)
27
VLCD0
—
28
CAP0
—
29
CAP1
—
30
VLCD2
—
31 to 34
COM0 to COM3
O
Common drive signal output to the liquid crystal display (LCD101)
35 to 49
SEG0 to SEG14
O
Segment drive signal output to the liquid crystal display (LCD101)
50
CE
I
Power failure detection signal input from the voltage detect (IC102) Normally: “H”
51
PULSE IN
I
Pulse meter input terminal (detecting a falling edge) Not used (open)
52
BEEP
O
Beep sound drive signal output terminal
53
CMP IN
I
Scan stop detect signal input terminal
54 to 56
PB1 to PB3
I
Initialize signal input for the destination select (fixed at “L” in this set)
KEY BOARD IC101
µ
PD17073GB-556-1A7
(SYSTEM CONTROLLER, LIQUID CRYSTAL DISPLAY DRIVER, KEY CONTROL)
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
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