Sony SRF-DR2000 Service Manual ▷ View online
– 10 –
Pin No.
Pin name
I/O
Description
69
A15
O
Address bus output to external memory.
70
A16
O
Address bus output to external memory.
71, 72
–
Not used (Open).
73
CS DEC
O
Chip select output to decoder (IC204).
74
CS RAM
O
Chip select output to RAM (IC202).
75
CS ROM
O
Chip select output to ROM (IC203).
76
DEC RES
O
Reset signal output to decoder (IC204).
77 - 78
–
Not used (Open).
_______
81
RESET
O
Reset signal output to DE-SCRAMBLE MICOM (IC301).
82
DD RDY
I
De-scramble end signal input.
83
CLK
O
Clock output to DE-SCRAMBLE MICOM (IC301).
84
DI
O
Data output to DE-SCRAMBLE MICOM (IC301).
85
DO
I
Data input from DE-SCRAMBLE MICOM (IC301).
86
INT
O
De-scramble request signal output.
87
POWER
O
Radio power supply ON/OFF control. “H” : Radio power ON
88
(+)
I
Tune (+) key input.
89
SRAM CHECK
I
SRAM check terminal.
90
A0 LCD
O
Communications with LCD module.
91
CS LCD
O
Communications with LCD module.
92
RES LCD
O
Communications with LCD module.
93
VDD
–
Power supply (+3V).
94
GND
–
Ground.
95
VDET
I
Low voltage (1.9V) DET. “L” : power OFF
96
POWER SW
I
Power ON/OFF key input.
97
EXT (IN)
I
External (Beep) signal input.
98
DATA LCD
O
Serial data output to LCD module.
99
EXT (OUT)
O
External (Beep) signal output.
100
SCL LCD
O
Serial clock output to LCD module.
– 11 –
IC204 (MSM9553) DECODER
Pin No.
Pin name
I/O
Description
1
MON
–
Not used (Open).
2
ADET IN
I
Analog signal input for test (connected ground).
3
AVDD
–
Power supply terminal for analog (+3.5V).
4
AGND
–
Ground terminal for analog (ground).
5
SG
O
Reference voltage terminal for analog.
6
AIN
I
FM multiplex signal input terminal.
________
7
XOUTC
–
Not used (Open).
8 - 14
MOUT0 - MOUT6
–
Not used (Open).
____
15
INT
O
interrupt signal output to MICOM (IC101).
___
16
WR
I
Write signal input terminal to internal register.
17
NC
–
Not used (Open).
___
18
RD
I
Ready signal input terminal to internal register.
19 - 26
D0 - D7
I/O
Data bus signal input/output terminal to internal register.
27
KGND
–
Ground terminal for digital.
28
DVDD
–
Power supply terminal for digital.
29
XTAL1
I
Oscillator connection terminal (8.192MHz).
30
XTAL2
O
Oscillator connection terminal (8.192MHz).
___
31
CS
I
Chip select signal input terminal.
32
XOUT
–
Not used (Open).
33 - 38
A0 - A5
I
Address signal input terminal to internal register.
39
NC
–
Not used (Open).
____
40
CLR
I
Internal register is reset at “L” setting power down status.
_____
41
IORD
–
Not used (Open).
______
42
IOWR
–
Not used (Open).
43,44
NC
–
Not used (Open).
– 12 –
IC301 MSM 69231-GS-2K (DE-SCRAMBLE MICOM)
Pin No.
Pin name
I/O
Description
1
–
Not used (Open).
2
DO
O
De-scramble data output.
3
DI
I
De-scramble data input.
4
CLK
I
Serial clock input.
–––––––––––––
5
RESET
I
Input signal input.
6, 7
–
Not used (Open).
8
INT
Input terminal for external de-scramble request singal.
9 – 13
–
Not used (Open).
–––––––––
14
OSC1
O
Main system clock oscillator (4.9152MHz).
15
OSC0
I
Main system clock oscillator (4.9152MHz).
16
GND
–
Ground.
17
OSC CONT
O
Clock oscillator control.
18 – 28
–
Not used (Open).
29
EA
I
Test terminal (Must be connected to VDD).
30 – 38
–
Not used (Open).
39
VDD
–
Power supply (+3.2V).
40
–
Not used (Open).
––––––––––––––––
41
DDRDY
O
De-scramble end signal output to external.
––––––––––––
42
BUSY
O
Busy signal output to external.
43, 44
–
Not used (Open).
IC501 (
µ
PD17015G) DTS MICROCOMPUTER
Pin No.
Pin name
I/O
Description
1
REQ
I
Communication request signal input.
2
READY
O
Output communication OK signal output.
3 - 5
PC1 - PC3
–
Not used (Open).
6
BEEP
–
Not used (Open).
7
DATA
I
PLL data input terminal.
8
CLK
I
PLL clock input terminal.
9, 10
PA2,PA3
–
Not used (Open).
11
CE
–
Not used (VDD connection).
12
XOUT
O
Clock oscillator connection terminal.
13
XIN
I
Clock oscillator connection terminal.
14
VDD
–
Power supply (+3V).
15
GND
–
Ground.
16
EO
O
PLL error output terminal.
17
VREG
–
Voltage REG terminal.
18
VCOH
–
Input local oscillator (VCO) output.
19
VCOL
–
Not used (Open).
20 - 28
LCD8 - LCD0
–
Not used (Open).
29 - 32
COM3 - COM0
–
Not used (Open).
33
VLCD1
–
Not used (Open).
34, 35
CAP1,CAP0
–
Not used (Open).
36
VLCD0
–
Not used (Open).
37, 38
PB0,PB1
–
Not used (Open).
– 13 –
–14 –
SRF-DR2000
4-2. BLOCK DIAGRAM
• Signal path.
F
: FM
J
: Multiplex
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