DOWNLOAD Sony SRF-DR2000 Service Manual ↓ Size: 3.98 MB | Pages: 23 in PDF or view online for FREE

Model
SRF-DR2000
Pages
23
Size
3.98 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
srf-dr2000.pdf
Date

Sony SRF-DR2000 Service Manual ▷ View online

– 7 –
2-3. MICOM BOARD, LCD1 REMOVAL
3
4
2
Claw
MICOM board
Claws
Cabinet (Front)
1
 Screws (1.7x5)
8
9
0
5
6
7
MICOM board
Holder (LCD)
LCD1
– 8 –
Adjustments Location :
SECTION 3
ELECTRICAL ADJUSTMENTS
FM Section
Setting :
VOLUME
: Maximum
1. Connect a capacitor (10
µ
F) between pin 1 of IC403 and ground.
2. Adjust RV401 for 76.2kHz – 75.8kHz reading on the frequency
counter.
• Repeat the procedures in each adjustment several times, and the
tracking adjustments should be finally the trimmer capacitors.
FM TRACKING ADJUSTMENT
Adjust for a maximum reading on level meter.
CT402
98.0MHz
FM VCO  Adjustment
Procedure :
FM RF signal
generator
TP FM IN
(BPF401 
1
 pin)
22.5kHz frequency 
deviation by 400Hz signal.
Output level : 
as low as possible
0.01  F
µ
set
16
phones jack
level meter
T401 : FM IF Alignment
RV401 : VCO Adjustment
CT402 : FM Tracking Adjustment
[MAIN BOARD]
(Side A)
IC403
RV401
1
5
6
10
R418
R428
76K
0.01
µ
F
1pF
10 
µ
F
DC5V
2.4k
1M
S
2SK193-E
Servicing tool
frequency counter
[MAIN BOARD] (Side A)
FM IF ALIGNMENT
Adjust for a maximum reading on level meter.
T401
10.7MHz
– 9 –
Pin No.
Pin name
I/O
Description
1
MUTE
O
Mute signal output.
2
BEEP
O
Beep signal output.
3
DEC INT
I
Interrupt signal input from decoder IC (IC204).
______
4
BUSY
I
Busy signal input from DE-SCRAMBLE MICOM (IC301).
5
F3
I
Function 3 key input.
6
F5
I
Function 5 key input.
7
F4
I
Function 4 key input.
8
(–)
I
Tune (–) key input.
9
VDD
Power supply (+3V).
10
VREF
Voltage reference terminal.
11
AGND
Ground for analog.
 12 - 15
AI0 - AI3
Not used (Ground connect).
16
GND
Ground.
17
VDD
Power supply (+3V).
18
READY PLL
I
Input PLL ready OK signal.
19
REQ PLL
O
PLL communication request output terminal.
20
DATA PLL
O
PLL serial data output terminal.
21
CLOCK PLL
O
PLL serial clock output terminal.
22
DI EEP
I
Data read input from EEPROM.
23
DO EEP
O
Data write output to EEPROM.
24
CLK EEP
O
Clock output to EEPROM.
25
CS EEP
O
Chip select output to EEPROM.
26
F2
I
Function 2 key input.
27
DISPLAY
I
Display (FM data) key input.
28
SAVE
I
Save key input.
29
F1
I
Function 1 key input.
30
ENTER
I
Enter key input.
31
BACK
I
Back key input.
32
FLA CLK
Not used (“H” level).
33
FLA DAT
Not used (“H” level).
____
34
RES
I
System reset terminal.
35
NMI
Not used (“H” level).
___
36
EA
I
Internal memory selection.    “H” : Active
37
VDD
Power supply (+3V).
38
OSC0
I
Main system clock oscillator (4.9152 MHz).
_____
39
OSS1
O
Main system clock oscillator (4.9152 MHz).
40
GND
Ground.
41
OSC CNT
O
Clock oscillator control.
42 - 46
Not used (Open).
___
47
RD
O
External memory read output.      “L” : Reading
___
48
WR
O
External memory write output.      “L” : Writing
49
Not used (Open).
50
ALE
O
Address latch signal output to external memory.
51 - 58
D0 - D7
I/O
Address / data bus input / output to external memory.
59 - 65
A8 - A14
O
Address  bus output to external memory.
66
Not used (Open).
67
VDD
Power supply (+3V).
68
GND
Ground.
SECTION 4
DIAGRAMS
4-1. EXPLANATION OF IC TERMINALS
IC101  MSM65587 (MAIN SYSTEM CONTROL)
– 10 –
Pin No.
Pin name
I/O
Description
69
A15
O
Address  bus output to external memory.
70
A16
O
Address  bus output to external memory.
71, 72
Not used (Open).
73
CS DEC
O
Chip select output to decoder (IC204).
74
CS RAM
O
Chip select output to RAM (IC202).
75
CS ROM
O
Chip select output to ROM (IC203).
76
DEC RES
O
Reset signal output to decoder (IC204).
77 - 78
Not used (Open).
_______
81
RESET
O
Reset signal output to DE-SCRAMBLE MICOM (IC301).
82
DD RDY
I
De-scramble end signal input.
83
CLK
O
Clock output to DE-SCRAMBLE MICOM (IC301).
84
DI
O
Data output to DE-SCRAMBLE MICOM (IC301).
85
DO
I
Data input from DE-SCRAMBLE MICOM (IC301).
86
INT
O
De-scramble request signal output.
87
POWER
O
Radio power supply ON/OFF control.     “H” : Radio power ON
88
 (+)
I
Tune (+) key input.
89
SRAM CHECK
I
SRAM check terminal.
90
A0 LCD
O
Communications with LCD module.
91
CS LCD
O
Communications with LCD module.
92
RES LCD
O
Communications with LCD module.
93
VDD
Power supply (+3V).
94
GND
Ground.
95
VDET
I
Low voltage (1.9V) DET.     “L” : power OFF
96
POWER SW
I
Power ON/OFF key input.
97
EXT (IN)
I
External (Beep) signal input.
98
DATA LCD
O
Serial data output to LCD module.
99
EXT (OUT)
O
External (Beep) signal output.
100
SCL LCD
O
Serial clock output to LCD module.
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