Sony SCD-X501ES Service Manual ▷ View online
37
SCD-X501ES
MAIN BOARD IC706 CXD2754Q (SA-CD/CD DECODER)
Pin No.
Pin Name
I/O
Description
1
CKVDD
Power supply (+1.8V) (for clock multiplier PLL)
2
CKVSS
Ground (for clock multiplier PLL)
3
MCKI
System clock (11.2896 MHz) signal input terminal
4, 5
CKSEL1, CKSEL0
System clock setting terminal Fixed at 11.2896 MHz in this set
6
VDIOCK
Power supply (+3.3V) (for clock I/O)
7
VSIOCK
Ground (for clock I/O)
8
EXCKO
External clock output terminal Not used (Open)
9
VDC0
Power supply (+1.8V) (for core)
10
VSC0
Ground (for core)
11 to 18
D0 to D7
Two-way data bus with the master controller
19
VDIO0
Power supply (+3.3V) (for I/O)
20
VSIO0
Ground (for I/O)
21 to 29
A0 to A8
Address signal input from the master controller
30
VDC1
Power supply (+1.8V) (for core)
31
VSC1
Ground (for core)
32
XINT
Interrupt signal output to the master controller
33
XCS
Chip select signal input from the master controller
34
XWAIT
Wait signal output to the master controller
35
XWR
Write enable signal input from the master controller
36
XRD
Read enable signal input from the master controller
37
XRST
System reset signal input from the reset signal generator and master controller “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
38
TRST
JTAG reset signal input from the reset signal generator and master controller “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39
TCK
Clock signal input terminal (for JTAG) Not used
40
TDI
Test data input terminal (for JTAG) Not used (Open)
41
TDO
Test data output terminal (for JTAG) Not used (Open)
42
TMS
Mode selection signal input terminal (for JTAG) Not used (Open)
43
SCANEN
Test terminal Not used
44 to 47
TEST0 to TEST3
Test terminal Not used (Open)
48
VDC2
Power supply (+1.8V) (for core)
49
VSC2
Ground (for core)
50 to 57
MNT0 to MNT7
Monitor terminal Not used (Open)
58
EXMNT
Extra monitor terminal Not used (Open)
59
VDIO1
Power supply (+3.3V) (for I/O)
60
VSIO1
Ground (for I/O)
61
SMUTE
Soft muting on/off control signal input from the master controller “H”: muting on
62 to 69
SUPDT0 to
SUPDT7
Not used (Open)
70
XSUPAK
Not used (Open)
71
FRAME
Not used (Open)
72
VDC3
Power supply (+1.8V) (for core)
73
VSC3
Ground (for core)
74
DSBCKAI
Bit clock signal input terminal (for DSD data output) Not used
75
DSBCKAO
Bit clock signal output terminal (for DSD data output) Not used (Open)
76
DSBCKASL
Bit clock signal input/output selection terminal (for DSD data output)
“L”: input (slave), “H”: output (master) Fixed at “H” in this set
“L”: input (slave), “H”: output (master) Fixed at “H” in this set
—
—
I
I
—
—
O
—
—
I/O
—
—
I
—
—
O
I
O
I
I
I
I
I
I
O
I
I
I
—
—
O
O
—
—
I
O
O
O
—
—
I
O
I
38
SCD-X501ES
Pin No.
Pin Name
I/O
Description
77
DSPHREFI
Phase reference signal input terminal (for DSD output phase modulation) Not used
78
DSPHREFO
Phase reference signal output to the D/A converter (for DSD output phase modulation)
79
VDDSD0
Power supply (+3.3V) (for DSD data output)
80
VSDSD0
Ground (for DSD data output)
81
DSADML
DSD data output terminal (for down mix L-ch) Not used (Open)
82
DSADMR
DSD data output terminal (for down mix R-ch) Not used (Open)
83
DSAL
DSD data output to the D/A converter (for front L-ch)
84
DSAR
DSD data output to the D/A converter (for front R-ch)
85
DSALS
DSD data output to the D/A converter (for surround L-ch)
86
DSARS
DSD data output to the D/A converter (for surround R-ch)
87
VDDSD1
Power supply (+3.3V) (for DSD data output)
88
VSDSD1
Ground (for DSD data output)
89
DSAC
DSD data output to the D/A converter (for center)
90
DSASW
DSD data output to the D/A converter (for sub woofer)
91
DSAEXTR
DSD data output terminal (for extra channel) Not used (Open)
92
VDC4
Power supply (+1.8V) (for core)
93
VSC4
Ground (for core)
94
CDLRCK
L/R sampling clock signal output to the D/A converter (for CD data output)
95
CDBCK
Bit clock signal output to the D/A converter (for CD data output)
96
PCMD1
CD data output to the D/A converter
97, 98
PCMD2, PCMD3
Decimation data output terminal Not used (Open)
99
BCK958
Bit clock signal output terminal Not used (Open)
100
DOUT958
Digital out signal output terminal
101
VDIO2
Power supply (+3.3V) (for I/O)
102
VSIO2
Ground (for I/O)
103 to 108
IOUT0 to IOUT5
DSD data output terminal Not used (Open)
109
VDC5
Power supply (+1.8V) (for core)
110
VSC5
Ground (for core)
111
IANCO
Ancillary data output terminal Not used (Open)
112
IFRM
Frame signal output terminal Not used (Open)
113
IOUT
Enable signal output terminal Not used (Open)
114
XSAK
Effective flag output terminal Not used (Open)
115
XSHD
Header flag output terminal Not used (Open)
116
IBCK
Bit clock signal output terminal Not used (Open)
117
XSRQ
Request signal input terminal Not used (Open)
118
IFULL
Data transmission hold request signal output terminal Not used (Open)
119
IEMPTY
Hi-speed transmission request signal output terminal Not used (Open)
120
VDIO3
Power supply (+3.3V) (for I/O)
121
VSIO3
Ground (for I/O)
122 to 125
MA0 to MA3
Address signal output to the SD-RAM
126
VDC6
Power supply (+1.8V) (for core)
127
VSC6
Ground (for core)
128 to 134
MA4 to MA10
Address signal output to the SD-RAM
135
MA11
Address signal output terminal Not used (Open)
136
BA0
Bank address signal output to the SD-RAM
137
BA1
Bank address signal output terminal Not used (Open)
138
XRAS
Row address strobe signal output to the SD-RAM
I
O
—
—
O
O
O
O
O
O
—
—
O
O
O
—
—
O
O
O
O
O
O
—
—
O
—
—
O
O
O
O
O
O
I
I
I
—
—
O
—
—
O
O
O
O
O
39
SCD-X501ES
Pin No.
Pin Name
I/O
Description
139
XCAS
Column address strobe signal output to the SD-RAM
140
VDC7
Power supply (+1.8V) (for core)
141
VSC7
Ground (for core)
142
XMWR
Write enable signal output to the SD-RAM
143
MCKE
Clock enable signal output to the SD-RAM
144
MMCK
Clock signal output to the SD-RAM
145
VDIO4
Power supply (+3.3V) (for I/O)
146
VSIO4
Ground (for I/O)
147
LDQM
Data mask (lower 8 bit) signal output to the SD-RAM
148
UDQM
Data mask (upper 8 bit) signal output to the SD-RAM
149 to 158
MD0 to MD9
Two-way data bus with the SD-RAM
159
VDC8
Power supply (+1.8V) (for core)
160
VSC8
Ground (for core)
161 to 166 MD10 to MD15
Two-way data bus with the SD-RAM
167
VDIO5
Power supply (+3.3V) (for I/O)
168
VSIO5
Ground (for I/O)
169 to 176
ADIO0 to ADIO7
A/D converter input/output terminal (for RF) No used (Open)
177
VDC9
Power supply (+1.8V) (for core)
178
VSC9
Ground (for core)
179
RFD
Binary RF signal output terminal No used (Open)
180
TESTI
Test terminal
181
PDAVDD
Power supply (+3.3V) (analog system for PLL-D/A)
182
PDAVSS
Ground (analog system for PLL-D/A)
183
PDAREF
Reference current output terminal (analog system for PLL-D/A)
184
PDAOUT
PLL-D/A output terminal
185
VCTL
VCO control voltage input terminal (for PLL)
186
PLLVDD
Power supply (+3.3V) (analog system for PLL)
187
PLLVSS
Ground (analog system for PLL)
188
RADVRT
Reference voltage (top side) input terminal (for RF A/D)
189
RADVDD
Power supply (+3.3V) (analog system for RF A/D)
190
RFIN
RF signal input from the SA-CD/CD RF amplifier
191
RADVSS
Ground (analog system for RF A/D)
192
RADVRB
Reference voltage (bottom side) input terminal (for RF A/D)
193
RFSWVSO
CD/DVD selection terminal (RFIN side)
194
RFSWVSI
CD/DVD selection terminal (ground side)
195
RFSWVDO
CD/DVD selection terminal (RFIN side)
196
RFSWVDI
CD/DVD selection terminal (power supply side)
197
SADVDD
Power supply (+3.3V) (analog system for servo A/D)
198
SADVSS
Ground (analog system for servo A/D)
199
ADIMNT
Not used (Open)
200
TEI
Tracking error signal input from the SA-CD/CD RF amplifier
201
FEI
Focus error signal input from the SA-CD/CD RF amplifier
202
PI
Pull-in signal input from the SA-CD/CD RF amplifier
203
SEI
Sled error signal input from the motor/coil driver
204
SP_RV
Spindle counter electromotive force input from the motor/coil driver
205
TSD-M
Thermal shut down signal output terminal Not used (Open)
206
VC0
Middle point voltage input from the motor/coil driver
O
—
—
O
O
O
—
—
O
O
I/O
—
—
I/O
—
—
I/O
—
—
O
I
—
—
O
O
I
—
—
I
—
I
—
I
O
I
O
I
—
—
O
I
I
I
I
I
O
I
40
SCD-X501ES
Pin No.
Pin Name
I/O
Description
207
SSIMON0
Not used (Open)
209
TE_F
Tracking error signal input from the SA-CD/CD RF amplifier (for internal Tracking zero crossing
signal generation)
signal generation)
210
VC1
Middle point voltage input from the motor/coil driver (for internal Tracking zero crossing signal
generation)
generation)
211
SDAVDD0
Power supply (+3.3V) (analog system for servo PWM)
212
SDAVSS0
Ground (analog system for servo PWM)
213, 214
TDOP, TDON
Tracking coil drive signal output to the motor/coil driver
215, 216
FDOP, FDON
Focus coil drive signal output to the motor/coil driver
217
VDC10
Power supply (+1.8V) (for core)
218
VSC10
Ground (for core)
219, 220 SLDOA, SLDOB
Sled motor drive signal output to the motor/coil driver
221, 222
SPDOA, SPDOB
Spindle motor drive signal output to the motor/coil driver
223
SDAVDD1
Power supply (+3.3V) (analog system for servo PWM)
224
SDAVSS1
Ground (analog system for servo PWM)
225
LOAD
Not used (Open)
226
JIT
Jitter value output to the master controller
227
VDC11
Power supply (+1.8V) (for core)
228
VSC11
Ground (for core)
229
DFCTI
Defect signal input from the SA-CD/CD RF amplifier
230
TZC
Tracking zero crossing signal input from the SA-CD/CD RF amplifier
231
MIRR
Mirror signal input from the SA-CD/CD RF amplifier
232
VDIO6
Power supply (+3.3V) (for I/O)
233
VSIO6
Ground (for I/O)
234
INLIM
Limit in detection switch input terminal
235
FGMODE
Spindle motor break signal output to the motor/coil driver
236
SSIMON1
Monitor signal input from the SA-CD/CD RF amplifier
237 to 241
GIO3 to GIO7
No used (Open)
242
VDC12
Power supply (+1.8V) (for core)
243
VSC12
Ground (for core)
244
SCS
Chip select signal output to the SA-CD/CD RF amplifier
245
SSI
Serial data input from the SA-CD/CD RF amplifier
246
SSO
Serial data output to the SA-CD/CD RF amplifier
247
SCK
Serial data transfer clock signal output to the SA-CD/CD RF amplifier
248
VDIO7
Power supply (+3.3V) (for I/O)
249
VSIO7
Ground (for I/O)
250 to 253 GIO12 to GIO15
No used (Open)
254
FG
Motor rotation speed detection signal input terminal Not used (Open)
255
M_ON
Motor on monitor terminal (for spindle control) Not used (Open)
256
LOCK
Lock monitor terminal (for spindle control) Not used (Open)
I
I
I
—
—
O
O
—
—
O
O
—
—
O
O
—
—
I
I
I
—
—
I
O
I
I/O
—
—
O
I
O
O
—
—
I/O
I
O
O
208
PI_F
Pull-in signial input from the SA-CD/CD RF amplifier
I
Click on the first or last page to see other SCD-X501ES service manuals if exist.