Sony SCD-CE775 Service Manual ▷ View online
73
SCD-CE775
Pin No.
Pin Name
I/O
Description
57
VDD
—
Power supply terminal (+3.3V) (digital system)
58
DSAR
O
DSD data (front R-ch) output to the digital filter (IC301)
59
GND
—
Ground terminal (digital system)
60
DSALS
O
DSD data (surround L-ch) output to the digital filter (IC302)
61
GND
—
Ground terminal (digital system)
62
DSARS
O
DSD data (surround R-ch) output to the digital filter (IC302)
63
VDD
—
Power supply terminal (+3.3V) (digital system)
64
DSAC
O
DSD data (center) output to the digital filter (IC303)
65
GND
—
Ground terminal (digital system)
66
DSASW
O
DSD data (sub woofer) output to the digital filter (IC303)
67
GND
—
Ground terminal (digital system)
68
PHREFI
I
Phase reference signal input terminal for DSD output phase modulation
69
PHREFO
O
Phase reference signal output for DSD output phase modulation to the digital filter (IC301 to
IC303)
IC303)
70
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output
“L”: input (slave), “H”: output (master) (fixed at “L” in this set)
“L”: input (slave), “H”: output (master) (fixed at “L” in this set)
71
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output Not used (open)
72
BCKAI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used
73, 74
TESTO
O
Output terminal for the test Not used
75
VDD
—
Power supply terminal (+3.3V) (digital system)
76
GND
—
Ground terminal (digital system)
77
TESTI
I
Input terminal for the test (normally: fixed at “L”)
78
TESTI
I
Input terminal for the test Not used
79
XSBSL2
I
HD mode selection signal input from the I/O expander (IC902)
80, 81
TESTI
I
Input terminal for the test Not used
82
XABSL1
I
HD mode selection signal input from the I/O expander (IC902)
83, 84
TESTO
O
Output terminal for the test Not used
85
DVCKI
I
11.2896 MHz clock signal input terminal
86
TESTI
I
Input terminal for the test Not used
87
GND
—
Ground terminal (digital system)
88
MCKI
I
Master clock signal (33.8688 MHz) input terminal
89
VDD
—
Power supply terminal (+3.3V) (digital system)
90
LRCK
O
L/R sampling clock signal (44.1kHz) output to the digital filter (IC301 to IC303)
91
CDDATAR
O
Serial data output terminal Not used (open)
92
CDDATAL
O
Serial data output to the digital filter (IC301)
93
CDDATASL
I
CD mode selection signal input from the I/O expander (IC902)
94
BCKI
I
Bit clock signal (2.8224 MHz) input from the CXD3068Q (IC509)
95
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the CXD3068Q (IC509)
96
CDDATAI
I
Serial data input from the CXD3068Q (IC509)
97
TESTI
I
Input terminal for the test (normally: fixed at “L”)
98
SMUTE
I
Muting on/off signal input from the CPU (IC901) “H”: muting on
99
XRST
I
Reset signal input from the I/O expander (IC902) “L”: reset
100
GND
—
Ground terminal (digital system)
74
SCD-CE775
•
MAIN BOARD IC901 CXP974096-001R (CPU)
Pin No.
Pin Name
I/O
Description
1
MODE DF
O
SACD/CD mode selection signal output to the muting circuit
“L”: CD mode, “H”: SACD mode
“L”: CD mode, “H”: SACD mode
2
AMUTE
O
Muting on/off signal output to the analog line circuit “L”: muting on
3
DOCTRL
O
Digital out on/off control signal output to the CXD3068Q (IC509)
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
4
LAT DAC
O
Serial data latch pulse signal output to the D/A converter Not used (open)
5
DATA DAC
O
Serial data output to the D/A converter Not used (open)
6
CLK DAC
O
Serial data transfer clock signal output to the D/A converter Not used (open)
7
FCS JMP 1
O
Focus jump 1 signal output to the BA5983FP (IC502)
8
FCS JMP 2
O
Focus jump 2 signal output to the BA5983FP (IC502)
9
SENS CD
I
Internal status (SENSE) signal input from the CXD3068Q (IC509)
10
XCS DRAM
O
Chip select signal output to the D-RAM Not used (pull up)
11
XCS IO
O
Chip select signal output to the I/O expander (IC902)
12
XCS DVD
O
Chip select signal output to the CXD1882R (IC701)
13
VSS
—
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the CXD1882R (IC701) and I/O expander (IC902)
22
INT0 DVD
I
Interrupt signal input from the CXD1882R (IC701)
23
INT1 DVD
I
Interrupt signal input from the CXD1882R (IC701)
24
T SENS
I
Disc tray status detection signal input from the table sensor (D10)
25
MON DVD
I
Monitor signal input terminal Not used (open)
26
DATA CD
O
Serial data output to the CXD3068Q (IC509)
27
XLAT CD
O
Serial data latch pulse signal output to the CXD3068Q (IC509)
28
A1IN
I
Sircs remote control signal input of the CONTROL A1II (J381)
29
COUT CD
I
Numbers of track counted signal input from the CXD3068Q (IC509)
30
IN SW
I
Loading in switch input terminal “L”: loading in Not used (fixed at “H”)
31
OUT SW
I
Loading out switch input terminal “L”: loading out Not used (fixed at “H”)
32
MIRR RF
I
Mirror signal input from the CXD3068Q (IC509)
33
SUBQ CD
I
Subcode Q data input from the CXD3068Q (IC509)
34
SCOR CD
I
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC509)
35
SQCLK CD
O
Subcode Q data reading clock signal output to the CXD3068Q (IC509)
36
—
—
Not used (open)
37
CLOK CD
O
Serial data transfer clock signal output to the CXD3068Q (IC509)
38
XRST
I
System reset signal input from the reset signal generator (IC905) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39
VSS
—
Ground terminal (digital system)
40
XTAL I
System clock input terminal (20 MHz)
41
EXTAL O
System clock output terminal (20 MHz)
42
VDD
—
Power supply terminal (+3.3V) (digital system)
43
SPDA
O
Spindle motor (M3) control signal output to the BA5912AFP (IC512)
44
APDO
O
Output terminal for offset adjustment of APEO (<z/. pin of CXD1882R (IC701))
45
MUTE DSD
O
Muting on/off signal output to the DSD decoder (IC801) and CXD9647R (IC803)
“H”: muting on
“H”: muting on
46
XMSLAT
O
Serial data latch pulse signal output to the DSD decoder (IC801)
47
READY DSD
I
Ready signal input from the DSD decoder (IC801) and CXD9647R (IC803) “L”: ready
48
SDIN DSD
I
Serial data input from the DSD decoder (IC801) and CXD9647R (IC803)
49
SOUT DSD
O
Serial data output to the DSD decoder (IC801) and CXD9647R (IC803)
75
SCD-CE775
Pin No.
Pin Name
I/O
Description
50
SCK DSD
O
Serial data transfer clock signal output to the DSD decoder (IC801) and CXD9647R (IC803)
51
LD ON
O
Laser diode on/off control signal output to the CXD1881R (IC001)
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
52
XDIS IO
O
Reset signal output to the I/O expander (IC902) “L”: reset
53
SDOUT
O
Serial data output to the MSM9202 (IC801)
54
SLK
O
Serial data transfer clock signal output to the MSM9202 (IC801)
55
VSS
—
Ground terminal (digital system)
56
REQ
O
Request signal output to the MSM9202 (IC801)
57
FCS BST
O
Focus boost signal output terminal Not used (open)
58
GFS DVD
I
Guard frame sync signal input from the CXD1882R (IC701)
59
LED DRV
O
LED drive signal output of the MULTI CHANNEL DECODING indicator (D803)
“H”: LED on
“H”: LED on
60
KEY 0
I
Key input terminal (A/D input)
S807 to S811 (H, X, x, EX-CHANGE, DISC SKIP) keys input
S807 to S811 (H, X, x, EX-CHANGE, DISC SKIP) keys input
61
KEY 1
I
Key input terminal (A/D input)
S801 to S805 (m, M, MENU, SACD/CD, MILTI/2CH) keys input
S801 to S805 (m, M, MENU, SACD/CD, MILTI/2CH) keys input
62
KEY 2
I
Key input terminal (A/D input) S812 to S816, S830 (TIME/TEXT, REPEAT, PROGRAM,
SHUFFLE, CONTINUE, PUSH ENTER) keys input
SHUFFLE, CONTINUE, PUSH ENTER) keys input
63
KEY 3
I
Key input terminal (A/D input)
S806, S817 to S821 (A OPEN/CLOSE, DISC 1/2/3/4/5) key input
S806, S817 to S821 (A OPEN/CLOSE, DISC 1/2/3/4/5) key input
64
JITTER
I
Jitter signal input
65
TE
I
Tracking error signal input from the CXD1881R (IC001)
66
SP ERR
I
Spindle motor backward voltage input terminal
67
FE/PI
I
Focus error signal input from the CXD1881R (IC001)
68
AVSS
—
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage input terminal (for A/D converter)
70
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
71
GFS CD
I
Guard frame sync signal input from the CXD3068Q (IC509)
72
SCLK CD
O
SENSE serial data reading clock signal output to the CXD3068Q (IC509)
73
1/2 LD
—
Not used (open)
74
FOK CD
I
Focus OK signal input from the CXD3068Q (IC509)
75
LOCK CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
XRF AD CE
O
Chip enable signal output to the A/D converter Not used (open)
77
SDCLK RF
O
Serial data transfer clock signal output to the CXD1881R (IC001)
78
EEPSIO
I/O
Two-way data bus with the EEPROM (IC903)
79
EEPSCL
O
Clock signal output to the EEPROM (IC903)
80
RXD
I
Serial data input from the RS-232C (for check)
81
TXD
O
Serial data output to the RS-232C (for check)
82
RM
I
Remote control signal input from the remote control receiver (IC802)
83
SDATA RF
I/O
Two-way data bus with the CXD1881R (IC001)
84
XWR
O
Write strobe signal output to the CXD1882R (IC701) and I/O expander (IC902)
85
XRD
O
Read strobe signal output to the CXD1882R (IC701) and I/O expander (IC902)
86
PWE
I
Flash writing switch (S902) input terminal “L”: writing impossible, “H”: writing possible
87
VDD
—
Power supply terminal (+3.3V) (digital system)
88
VSS
—
Ground terminal (digital system)
89 to 91
A0 to A2
O
Address signal output to the CXD1882R (IC701) and I/O expander (IC902)
76
SCD-CE775
Pin No.
Pin Name
I/O
Description
92 to 96
A3 to A7
O
Address signal output to the CXD1882R (IC701)
97
INIT DF
O
Initial signal output to the digital filter Not used
98
LATCH DF
O
Latch signal output to the digital filter (IC301 to IC303)
99
SHIFT DF
O
Shift signal output to the digital filter (IC301 to IC303)
100
SCDATA DF
O
Serial data output to the digital filter (IC301 to IC303)
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