Sony SCD-C555ES Service Manual ▷ View online
50
SCD-C555ES
Description
Write enable output terminal for SDRAM.. Connect it to XWE terminal of DRAM.
Column address strobe output terminal for SDRAM. Connect it to CAS terminal of SDRAM.
Row address strobe output terminal for SDRAM. Connect it to RAS terminal of SDRAM.
Power terminal for input and output. Supply +3.3 V.
Keep open.
Address output terminal for SDRAM ÅiMSBÅj.
Address output terminal for SDRAM.
Ground terminal for core.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Power terminal for core. Supply +2.5 V.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Ground terminal for input and output.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM. (LSB).
Power terminal for input and output. Supply +3.3 V.
Data request output terminal that inputs into front end processor.
Input terminal for header flag that is output from front end processor.
Input terminal for data transmission clock that is output from front end processor.
Input terminal for data effective flag that is output from front end processor.
Input terminal for error flag that is output from front end processor.
Input terminal for stream data that is output from front end processor (LSB).
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor (MSB).
I/O
O
O
O
—
O
O
O
—
O
O
—
O
O
O
O
—
O
O
O
O
—
O
I
I
I
I
I
I
I
I
I
I
I
I
Pin Name
XWE
XCAS
XRAS
VDIO
TESTO
A11
A10
VSC
A9
A8
VDC
A7
A6
A5
A4
VSIO
A3
A2
A1
A0
VDIO
XSRQ
XSHD
SDCK
XSAK
SDEF
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Pin No.
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
51
SCD-C555ES
• MAIN BOARD IC803 CXD9647 (DSD DSP)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
—
O
O
O
I
I
I
—
O
O
O
O
O
O
O
O
Ipd
Ipd
O
—
Ipd
—
I
O
—
—
Ipd
O
Ipd
O
—
I
—
I
—
I
—
I
—
I
—
I
—
O
O
O
I
O
Description
Power terminal. Supply +3.3 V.
Output enable terminal for microcomputer serial communication. When using tri-state buffer externally, activates
by this terminal. When outputs “MSDATO”, “L” is shown.
Output ready flag for microcomputer serial communication. When completing, outputs “L”. Open drain.
Data output terminal for microcomputer serial communication. Hi-Z except for output.
Data input terminal for microcomputer serial communication. Inputs data and address with serial from
microcomputer.
Shift clock input terminal for microcomputer serial communication. Imports and shifts serial input data by setting up
clock that inputs into this terminal. When reading out, read data change by falling of clock that inputs into this terminal.
Latch input terminal for microcomputer serial communication. Latches address and data at falling this signal.
Ground terminal
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing (pull down). Keep open or fix “L”.
Input terminal for testing (pull down). Keep open or fix “L”.
Output terminal for testing. Keep open.
Ground terminal
Input terminal for testing (pull down). Keep open or fix “L”.
Ground terminal
Input terminal for testing. Fix “L”.
Output terminal for testing. Keep open.
Power terminal. Supply +3.3 V.
Ground terminal
Input terminal for testing (pull down). Keep open or fix “L”.
Bit clock output terminal for DSD data phase modulation input. Outputs 128 Fs.
Input terminal for testing (pull down). Keep open or fix “L”.
Bit clock output terminal for DSD data normal input or phase reference signal output terminal for phase modulation
input. Outputs 64 Fs.
Ground terminal
DSD data input terminal 1
Ground terminal
DSD data input terminal 2
Power terminal. Supply +3.3 V.
DSD data input terminal 3
Ground terminal
DSD data input terminal 4
Ground terminal
DSD data input terminal 5
Power terminal. Supply +3.3.V.
DSD data input terminal 6
Ground terminal
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Output terminal for testing. Keep open.
Pin Name
VDD
XMSDOE
MSREADY
MSDATO
MSDATI
MSCK
XMSLAT
GND
TESTO
TESTO
TESTO
TESTO
TESTO
TESTO
TESTO
TESTO
TESTI
TESTI
TESTO
GND
TESTI
GND
TESTI
TESTO
VDD
GND
TESTI
FS128
TESTI
FS64
GND
DSI1
GND
DSI2
VDD
DSI3
GND
DSI4
GND
DSI5
VDD
DSI6
GND
TESTO
TESTO
TESTO
TESTI
TESTO
Ipd : Pull douwn input
52
SCD-C555ES
Description
Input terminal for testing. Fix “L”.
Ground terminal
Power terminal. Supply +3.3.V.
Output terminal for testing. Keep open.
Ground terminal
Output terminal for testing. Keep open.
Ground terminal
Channel L DSD data output terminal
Power terminal. Supply +3.3.V.
Channel R DSD data output terminal
Ground terminal
Channel LS DSD data output terminal
Ground terminal
Channel RS DSD data output terminal
Power terminal. Supply +3.3 V.
Channel C DSD data output terminal
Ground terminal
Channel SW DSD data output terminal
Ground terminal
Phase reference signal input terminal for DSD output phase modulation
Phase reference signal output terminal for DSD output phase modulation
Bit clock input/output selection terminal for DSD data output. “L” is input (slave) and “H” is output (Master).
Bit clock output terminal for DSD data output. When BCKASL is “H”, bit clock is output from this terminal.
Bit clock input terminal for DSD data output. When BCKASL is “L”, input bit clock into this terminal.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Power terminal. Supply +3.3 V.
Ground terminal
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Ground terminal
Master clock input terminal. Inputs clock with 768 Fs (33.8688 MHz).
Power terminal. Supply +3.3 V.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing (pull down). Keep open or fix “L”.
Soft mute terminal. Soft-mutes audio output with “”H” and releases it with “L”.
Reset terminal. Resets entire IC on “L”. Clock that is output from FS128 and FS64 of output terminal, doesn’t
stop in resetting.
Ground terminal
Pin No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
TESTI
GND
VDD
TESTO
GND
TESTO
GND
DSAL
VDD
DSAR
GND
DSALS
GND
DSARS
VDD
DSAC
GND
DSASW
GND
PHREFO
PHREFI
BCKASL
BCKAO
BCKAI
TESTO
TESTO
VDD
GND
TESTI
TESTI
TESTI
TESTI
TESTI
TESTI
TESTO
TESTO
TESTI
TESTI
GND
MCKI
VDD
TESTO
TESTO
TESTO
TESTI
TESTI
TESTI
TESTI
TESTI
SMUTE
XRST
GND
I/O
I
—
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
I
I
O
I
O
O
—
—
I
I
I
I
I
I
O
O
I
I
—
I
—
O
O
O
I
I
I
I
Ipd
I
I
—
Ipd : Pull douwn input
53
SCD-C555ES
• MAIN BOARD IC901 CXP974F096R (MECHA CONTROL)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
I/O
O
O
O
O
O
O
O
O
I
O
O
O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
O
O
I
I
I
I
I
I
I
O
—
O
I
—
I
O
—
O
O
O
O
I
I
O
O
I
Description
SACD/CD mode select signal “L” : CD mode “H” : SACD mode
Analog mute “L” : muting
Digital out control “L” : digital out off “H” : digital out on
DAC latch
DAC data
DAC clock
Focus jump 1
Focus jump 2
CD DSP Internal status (SENSE) signal
SRAM chip select (not used)
IO Expander chip select
DVD-Decoder chip select
Ground terminal (digital system)
Parallel data bus
Parallel data bus
Parallel data bus
Parallel data bus
Parallel data bus
Parallel data bus
Parallel data bus
Parallel data bus
DVD-Decoder interrupt
DVD-Decoder interrupt
Changer table slit sensor interrupt
DVD decoder monitor (not used)
CD DSP data
CD DSP latch
Control A1 input interrupt
CD-DSP COUT signal
Tray (CHANGER panel) IN SW “L” : loading in
Tray (CHANGER panel) OUT SW “L” : loading out
MIRR signal
CD-DSP sub Q signal input
SCOR
CD-DSP sub Q read clock
Not used
CD DSP clock
Reset input
Ground terminal
System clock input (20MHz)
System clock output (20MHz)
Power supply terminal (+3.3V)(digital system)
Laser diode on/off control signal “L” : laser diode off, “H” : laser diode on
IO Expander reset signal
DSD Decoder mute “H” : muting
DSD Decoder serial latch
DSD Decoder Ready signal “L” : ready
DSD Decoder serial in
DSD Decoder serial out
DSD Decoder serial clock
Display controller BUSY signal
Pin Name
MODE_DF
AMUTE
DOCTRL
LAT_DAC
DATA_DAC
CLK_DAC
FCS_JMP_1
FCS_JMP_2
SENS_CD
XCS2
XCS_IO
XCS_DVD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
INT0_DVD
INT1_DVD
T_SENS
MON_DVD
DATA_CD
XLAT_CD
A1IN
COUT_CD
IN_SW
OUT_SW
MIRR
SQSO
SCOR
SQCK
PF6
CLOK_CD
XRST
VSS
XTAL
XEXTAL
VDD
LDON
XDIS_IO
MUTE_DSD
XMSLAT
READY_DSD
SDIN_DSD
SDOUT_DSD
SCK_DSD
BUSY_DP
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