DOWNLOAD Sony SCD-C555ES Service Manual ↓ Size: 16.88 MB | Pages: 93 in PDF or view online for FREE

Model
SCD-C555ES
Pages
93
Size
16.88 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
scd-c555es.pdf
Date
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48
SCD-C555ES
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Pin Name
SUPDT7
XSUPAK
VSC
TESTO
TESTI
TESTI
TESTO
VDC
TESTO
TESTO
BCKASL
VSDSD
BCKAI
BCKAO
PHREFI
PHREFO
ZDFL
DSAL
ZDFR
DSAR
VDDSD
ZDFC
DSAC
ZDFLFE
DSALFE
VSDSD
ZDFLS
DSALS
ZDFRS
DSARS
VDDSD
TESTO
TESTO
VSC
TESTO
TESTO
VDC
TESTO
TESTO
VSIO
TESTO
TESTI
TESTI
VDIO
TESTO
TESTO
TESTO
I/O
O
O
—
O
I
I
O
—
O
O
I
—
I
O
I
O
O
O
O
O
—
O
O
O
O
—
O
O
O
O
—
O
O
—
O
O
—
O
O
—
O
I
I
—
O
O
O
Description
Output terminal for supplementary data (MSB).
Output terminal for supplementary data acknowledge.
Ground terminal for core.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Output terminal for testing. Keep open.
Power terminal for core. Supply +2.5 V.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Bit clock input/output selection terminal for DSD data output. “L” is input (slave) and “H” is output (Master).
Ground terminal for DSD data output.
Bit clock input terminal for DSD data output. When BCKASL is “L”, input bit clock into this terminal.
Bit clock output terminal for DSD data output. When BCKASL is “H”, bit clock is output from this terminal.
Phase reference signal input terminal for DSD output phase modulation.
Phase reference signal output terminal for DSD output phase modulation.
Zero data detection flag in channel R (when setting microcomputer). When no sound data keeps for 300 msec,
this flag changes to “H”.
Output terminal for DSD data in channel L.
Zero data detection flag in channel L (when setting microcomputer). When no sound data keeps for 300 msec,
this flag changes to “H”.
Output terminal for DSD data in channel R.
Power terminal for DSD data output. Supply a +3.3 V that is separated from other digital power source.
Zero data detection flag in channel C (when setting microcomputer). When no sound data keeps for 300 msec,
this flag changes to “H”.
DSD data output terminal in channel C.
Zero data detection flag in channel LFE (when setting microcomputer). When no sound data keeps for 300
msec, this flag changes to “H”.
DSD data output terminal in channel LFE.
Ground terminal for DSD data output.
Zero data detection flag in channel LS (when setting microcomputer). When no sound data keeps for 300 msec,
this flag changes to “H”.
DSD data output terminal in channel LS.
Zero data detection flag in channel RS (when setting microcomputer). When no sound data keeps for 300 msec,
this flag changes to “H”.
DSD data output terminal in channel RS.
Power terminal for DSD data output. Supply a +3.3 V that is separated from other digital power source.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Ground terminal for core.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Power terminal for core. Supply +2.5 V.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Ground terminal for input and output.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Power terminal for input and output. Supply +3.3 V.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
49
SCD-C555ES
Pin No.
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
Pin Name
VSC
TESTI
TESTI
TESTI
TESTO
VDC
TESTI
TESTI
TESTI
TESTI
TESTI
TESTI
VSIO
TESTI
TESTI
TESTI
VDIO
WAD0
WAD1
WAD2
WAD3
VSIO
VSC
WAD4
WAD5
WAD6
WAD7
VDC
TESTI
WCK
WAVDD
WAVDD
WARFI
WAVRB
WAVSS
WAVSS
VSIO
DQ7
DQ6
DQ5
DQ4
VDIO
DQ3
DQ2
DQ1
DQ0
VSIO
DCLK
DCKE
I/O
—
I
I
Ipu
O
—
I
I
I
I
I
I
—
I
I
I
—
I
I
I
I
—
—
I
I
I
I
I
I
I
—
—
Ai
Ai
—
—
—
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
—
O
O
Description
Ground terminal for core.
Input terminal for testing. Fix “H”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “H”.
Input terminal for testing. Keep open.
Power terminal for core. Supply +2.5 V.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Ground terminal for input and output.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Power terminal for input and output. Supply +3.3 V.
External A/D data input terminal for PSP physical disc marking detection (LSB). This terminal is not used for
internal A/D but is used only for connecting A/D to outside.
External A/D data input terminal for PSP physical disc marking detection.
External A/D data input terminal for PSP physical disc marking detection.
External A/D data input terminal for PSP physical disc marking detection.
Ground terminal for input and output.
Ground terminal for core.
External A/D data input terminal for PSP physical disc marking detection.
External A/D data input terminal for PSP physical disc marking detection.
External A/D data input terminal for PSP physical disc marking detection.
External A/D data input terminal for PSP physical disc marking detection (MSB).
Power terminal for core. Supply +2.5 V.
Input terminal for testing. Fix “L”.
Operation clock for PSP physical disc marking detection. Input PLL clock that supports 1T of RF.
A/D power terminal for PSP physical disc marking detection. Supply +2.5 V that is separated from other digital
power source.
A/D power terminal for PSP physical disc marking detection. Supply +2.5 V that is separated from other digital
power source.
Analog RF signal input terminal for PSP physical disc marking detection.Full scale is 2.5 V.
A/D bottom reference terminal for PSP physical disc marking detection. Voltage that is input into this terminal,
becomes a full scale at ground side of A/D.
A/D ground terminal for PSP physical disc marking detection.
A/D ground terminal for PSP physical disc marking detection.
Ground terminal for input and output.
Input and output terminal for SDRAM data (MSB).
Input and output terminal for SDRAM data.
Input and output terminal for SDRAM data.
Input and output terminal for SDRAM data.
Power terminal for input and output. Supply +3.3 V.
Input and output terminal for SDRAM data.
Input and output terminal for SDRAM data.
Input and output terminal for SDRAM data.
Input and output terminal for SDRAM data.
Ground terminal for input and output.
Clock output terminal for SDRAM.
Clock enable output terminal for SDRAM.
50
SCD-C555ES
Description
Write enable output terminal for SDRAM.. Connect it to XWE terminal of DRAM.
Column address strobe output terminal for SDRAM. Connect it to CAS terminal of SDRAM.
Row address strobe output terminal for SDRAM. Connect it to RAS terminal of SDRAM.
Power terminal for input and output. Supply +3.3 V.
Keep open.
Address output terminal for SDRAM ÅiMSBÅj.
Address output terminal for SDRAM.
Ground terminal for core.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Power terminal for core. Supply +2.5 V.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Ground terminal for input and output.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM.
Address output terminal for SDRAM. (LSB).
Power terminal for input and output. Supply +3.3 V.
Data request output terminal that inputs into front end processor.
Input terminal for header flag that is output from front end processor.
Input terminal for data transmission clock that is output from front end processor.
Input terminal for data effective flag that is output from front end processor.
Input terminal for error flag that is output from front end processor.
Input terminal for stream data that is output from front end processor (LSB).
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor.
Input terminal for stream data that is output from front end processor (MSB).
I/O
O
O
O
—
O
O
O
—
O
O
—
O
O
O
O
—
O
O
O
O
—
O
I
I
I
I
I
I
I
I
I
I
I
I
Pin Name
XWE
XCAS
XRAS
VDIO
TESTO
A11
A10
VSC
A9
A8
VDC
A7
A6
A5
A4
VSIO
A3
A2
A1
A0
VDIO
XSRQ
XSHD
SDCK
XSAK
SDEF
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Pin No.
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
51
SCD-C555ES
• MAIN BOARD  IC803  CXD9647 (DSD DSP)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
—
O
O
O
I
I
I
—
O
O
O
O
O
O
O
O
Ipd
Ipd
O
—
Ipd
—
I
O
—
—
Ipd
O
Ipd
O
—
I
—
I
—
I
—
I
—
I
—
I
—
O
O
O
I
O
Description
Power terminal. Supply +3.3 V.
Output enable terminal for microcomputer serial communication. When using tri-state buffer externally, activates
by this terminal. When outputs “MSDATO”, “L” is shown.
Output ready flag for microcomputer serial communication. When completing, outputs “L”. Open drain.
Data output terminal for microcomputer serial communication. Hi-Z except for output.
Data input terminal for microcomputer serial communication. Inputs data and address with serial from
microcomputer.
Shift clock input terminal for microcomputer serial communication. Imports and shifts serial input data by setting up
clock that inputs into this terminal. When reading out, read data change by falling of clock that inputs into this terminal.
Latch input terminal for microcomputer serial communication. Latches address and data at falling this signal.
Ground terminal
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing (pull down). Keep open or fix “L”.
Input terminal for testing (pull down). Keep open or fix “L”.
Output terminal for testing. Keep open.
Ground terminal
Input terminal for testing (pull down). Keep open or fix “L”.
Ground terminal
Input terminal for testing. Fix “L”.
Output terminal for testing. Keep open.
Power terminal. Supply +3.3 V.
Ground terminal
Input terminal for testing (pull down). Keep open or fix “L”.
Bit clock output terminal for DSD data phase modulation input. Outputs 128 Fs.
Input terminal for testing (pull down). Keep open or fix “L”.
Bit clock output terminal for DSD data normal input or phase reference signal output terminal for phase modulation
input. Outputs 64 Fs.
Ground terminal
DSD data input terminal 1
Ground terminal
DSD data input terminal 2
Power terminal. Supply +3.3 V.
DSD data input terminal 3
Ground terminal
DSD data input terminal 4
Ground terminal
DSD data input terminal 5
Power terminal. Supply +3.3.V.
DSD data input terminal 6
Ground terminal
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Output terminal for testing. Keep open.
Pin Name
VDD
XMSDOE
MSREADY
MSDATO
MSDATI
MSCK
XMSLAT
GND
TESTO
TESTO
TESTO
TESTO
TESTO
TESTO
TESTO
TESTO
TESTI
TESTI
TESTO
GND
TESTI
GND
TESTI
TESTO
VDD
GND
TESTI
FS128
TESTI
FS64
GND
DSI1
GND
DSI2
VDD
DSI3
GND
DSI4
GND
DSI5
VDD
DSI6
GND
TESTO
TESTO
TESTO
TESTI
TESTO
Ipd : Pull douwn input
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