Sony SCD-C555ES Service Manual ▷ View online
42
SCD-C555ES
IC904 BU2500FV-E2
(MAIN BOARD)
1
2
3
4
5
6
7
8
16
17
18
19
20
15
14
13
12
11
10
9
8bit R-2R
D/A CONV.
8bit R-2R
D/A CONV.
8bit LATCH
8bit LATCH
D0
1
2
3
4
5
6
D7
D8
9
1
0
D11
12bit
SHIFT REGISTER
ADD.
DECODER
D/A
D/A
L
L
D/A
L
D/A
L
D/A
L
D/A
L
D/A
L
D/A
D/A
D/A
L
LL
Ch3
4
5
6
7
8
9
10
Ch2
1
12
11
VSS
(VrefL)
VDD
(VrefH)
VCC
D0
A03
A04
A05
A06
A07
A08
A09
A010
A011
A012
LD
CLK
DI
A01
A02
GND
43
SCD-C555ES
IC906 TC74VHCT32AFT
(MAIN BOARD)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
4B
4A
4Y
3B
3A
3A
3Y
GND
2Y
2B
2A
1Y
1B
1A
IC812, IC813 SN74LV245PWR
(MAIN BOARD)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A1
DIR
A2
A3
A4
A5
A6
A7
A8
GND
ENABLE
G
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
IC509 CXD3008Q
(MAIN BOARD)
26 27
28
29 30 31 32 33 34
35 36 37
38 39 40
TES1
SE
FE
VC
TFDR
DVSS1
FRDR
FFDR
TRDR
SRDR
SFDR
DVDD1
FST0
SSTP
TES1
80 79 78 77 76
75 74 73
72 71 70 69 68 67 66
XTSL
PCMD
BCK
EMPH
XOLT
XTA1
XTA0
SOUT
SOCK
SQSO
SQCK
SCSY
EXCK
EXCK
DVSS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
XRST
VDD
MDP
LOCK
PWM1
DFCT
MIRR
COUT
DVSS
WDCK
FDK
SCOR
C2P0
XPCK
XUGF
WFCK
ATSK
SENS
CLOK
XLAT
DATA
SENS
CLOK
XLAT
DATA
MUTE
SCLK
GFS
C4M
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
65
64
47
46
45
44
43
42
41
LRCK
DOUT
VPC0
ASYE
MD2
FIL0
CLTV
ASY0
ASY1
RFAC
AVSS1
FIL1
PCO
DVDD2
BIAS
V16M
CE
TE
RFDC
AD10
AVSS0
1GEN
AVDD
CLOCK
GENERATOR
ASYMMETY
CORRECTOR
DIGITAL
PLL
EFM
DEMODURATOR
DIGITAL
PLL
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
SERVO
INTERFACE
SUB
CODE
PROCESSOR
DIGITAL
OUT
ERROR
CORRECTOR
32K
RAM
D/A
INTERFACE
MIRR
DFCT
FOK
OP
AMP
ANALOG
SW
A/D
CONVERTER
FOCUS SERVO
TRACKING
SERVO
SERVO DSP
SLED PWM
GENERATOR
TRACKING PWM
GENERATOR
FOCUS PWM
GENERATOR
PWM GENERATOR
SLED SERVO
44
SCD-C555ES
4-26. IC PIN FUNCTION DESCRIPTION
• MAIN BOARD IC701 CXD1882R (DVD DECODER)
Pin No.
1, 2
3
4
5
6
7
8
9 to 14
15
16
17
18
19
20, 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59, 60
I/O
I/O
—
I/O
I
—
I
—
I
—
O
I
I
I
O
—
I
O
—
O
O
—
O
O
O
O
—
O
O
—
O
—
O
O
O
—
O
O
O
O
—
O
O
—
O
—
I
O
O
I
I/O
—
I
Description
Two-way data bus with the CPU (IC901) and expander (IC902)
Ground terminal (digital system)
Two-way data bus with the CPU (IC901) and expander (IC902)
Address signal input from the CPU (IC901)
Power supply terminal (+3.3V) (digital system)
Address signal input from the CPU (IC901)
Power supply terminal (+5V)
Address signal input from the CPU (IC901)
Ground terminal (digital system)
Wait signal output terminal Not used (open)
Read strobe signal input from the CPU (IC901)
Write strobe signal input from the CPU (IC901)
Chip select signal input from the CPU (IC901)
Interrupt signal output to the CPU (IC901)
Power supply terminal (+3.3V) (digital system)
Not used (open)
Stream data signal output to the DSD decoder (IC801)
Ground terminal (digital system)
Error flag signal output to the DSD decoder (IC801)
Stream data signal output to the DSD decoder (IC801)
Power supply terminal (+5V) (digital system)
Not used (open)
Stream data signal output to the DSD decoder (IC801)
Not used (open)
Stream data signal output to the DSD decoder (IC801)
Ground terminal (digital system)
Not used (open)
Stream data signal output to the DSD decoder (IC801)
Power supply terminal (+3.3V) (digital system)
Not used (open)
Power supply terminal (+5V) (digital system)
Stream data signal output to the DSD decoder (IC801)
Not used (open)
Stream data signal output to the DSD decoder (IC801)
Ground terminal (digital system)
Not used (open)
Stream data signal output to the DSD decoder (IC801)
Not used (open)
Serial data transfer acknowledge signal output to the DSD decoder (IC801)
Power supply terminal (+5V) (digital system)
Serial data transfer clock signal output to the DSD decoder (IC801)
Header flag signal output to the DSD decoder (IC801)
Power supply terminal (+3.3V) (digital system)
Not used (pull up)
Ground terminal (digital system)
Serial data transfer request signal input from the DSD decoder (IC801)
Not used (pull up)
Not used (pull up)
Not used (fixed at “H” )
Not used (pull up)
Power supply terminal (+5V) (digital system)
Not used (fixed at “H” )
Pin Name
D5, D6
VSS
D7
A0
VDD
A1
VDD5V
A2 to A7
VSS
XWAIT
XRD
XWR
XCS
XINT0, XINT1
VDD
XHRS
HDB7
VSS
HDB8
HDB6
VDDS
HDB9
HDB5
HDBA
HDB4
VSS
HDBB
HDB3
VDD
HDBC
VDDS
HDB2
HDBD
HDB1
VSS
HDBE
HDB0
HDBF
XACK
VDDS
DCK
XSHDR0
VDD
REDY
VSS
REQUEST
HINT
XS16
HA1
XPDI
VDDS
HA0, HA2
45
SCD-C555ES
Pin No.
61
62, 63
64
65
66 to 69
70
71
72
73 to 75
76
77
78
79, 80
81
82 to 87
88
89
90
91
92
93
94
95
96, 97
98
99
100
101, 102
103
104 to 106
107
108
109
110
111
112
113, 114
115
116
117
118, 119
120
121
122, 123
124
125
126, 127
128, 129
130
131
Pin Name
VSS
HCS0, HCS1
VDD
DASP
MDB0 to MDB3
VSS
MDB4
VDD5V
MDB5 to MDB7
XMWR
VDD
XRAS
MA0, MA1
VSS
MA2 to MA7
VDD
MA8
VSS
MA9/MNT0
MA10/MNT1
MA11/MNT2
XMOE
XCAS
MDB8, MDB9
VSS
MDBA
VDD
MDBB, MDBC
VDD5V
MDBD to MDBF
GFS
VSS
APEO
VDD
DASYO
GNDA5
ASF1, AFS2
DASYI
RFDCC
RF IN
VCCA5, VCCA4
VCOR1
VCOIN
GNDA4, GNDA3
LPF5
VC1
LPF2, LPF1
VCCA3, VCCA2
PDO
PDHVCC
I/O
—
I
—
I/O
I/O
—
I/O
—
I/O
O
—
O
O
—
O
—
O
—
O
O
O
O
O
I/O
—
I/O
—
I/O
—
I/O
O
—
O
—
O
—
—
I
I
I
—
—
I
—
O
I
I
—
O
I
Description
Ground terminal (digital system)
Not used (open)
Power supply terminal (+3.3V) (digital system)
Not used (pull up)
Two-way data bus with the D-RAM (IC706)
Ground terminal (digital system)
Two-way data bus with the D-RAM (IC706)
Power supply terminal (+5V)
Two-way data bus with the D-RAM (IC706)
Write enable signal output to the D-RAM (IC706)
Power supply terminal (+3.3V) (digital system)
Row address strobe signal output to the D-RAM (IC706)
Address signal output to the D-RAM (IC706)
Ground terminal (digital system)
Address signal output to the D-RAM (IC706)
Power supply terminal (+3.3V) (digital system)
Address signal output to the D-RAM (IC706)
Ground terminal (digital system)
Address signal output to the D-RAM (IC706)
RF data signal output terminal for disc mark detection
Clock signal output terminal for disc mark detection
Monitor signal output to the CPU (IC901)
Output enable signal output to the D-RAM (IC706)
Column address strobe signal output to the D-RAM (IC706)
Two-way data bus with the D-RAM (IC706)
Ground terminal (digital system)
Two-way data bus with the D-RAM (IC706)
Power supply terminal (+3.3V) (digital system)
Two-way data bus with the D-RAM (IC706)
Power supply terminal (+5V)
Two-way data bus with the D-RAM (IC706)
Guard frame sync signal output to the CPU (IC901)
Ground terminal (digital system)
Absolute phase error signal output
Power supply terminal (+3.3V) (digital system)
RF binary signal output
Ground terminal (analog system)
Filter connected terminal for selection the constant asymmetry compensation
Analog signal input after integrated from the RF binary signal
Input terminal for adjusting DC cut high-pass filter for RF signal
RF signal input from the CXD1881R (IC001)
Power supply terminal (+3.3V) (analog system)
VCO oscillating range setting resistor connected terminal
VCO input terminal
Ground terminal (analog system)
Signal output from the operation amplifier from PLL loop filter
Middle point voltage (+1.65V) input terminal
Inverted signal input to the operation amplifier from PLL loop filter
Power supply terminal (+3.3V) (analog system)
Signal output from the charge pump for phase comparator
Middle point voltage input terminal for RF PLL
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