Sony SCD-C222ES Service Manual ▷ View online
61
SCD-C222ES
IC701
CXD1882R-1
133
134
135
136
137
138
139
140
141
142
143
144
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
165
166
164
167
168
169
170
172
173
174
175
176
1
171
145
SPINDLE
CONTROL
CD-
DSP
I/F
DAC
I/F
132131130129128
123122
119118
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
22
CPU IF, DMA CONTROLLER
121120
117116115114113112111110109108107
106105104103102101100 99 98 97 96
95 94 93 92 91 90 89
88
87
126125
124
PLL
VCO
127
SYNC DETECT
EFM+
DEMODULATOR
SELECTOR ID
DETECT
SUBCODE
DEINTERLEAVE & ECC
SYNC
CONTROL
ATAPI
REGISTERS
DMA
CONTROLLER
PRIORITY RESOLVE
& SEQUENSOR
DVD
MAIN DATA
ECC & EDC
CD-ROM
MAIN DATA
ECC & EDC
ATAPI
PACKET
FIFO
86
85
84
83
82
81
80
79
78
75
74
73
72
71
70
69
68
67
66
77
76
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
DESCRAMBLE
RF ASYMMETRY
HOST I/F
ATAPI
OR
DMA
OR
VIDEO
DMA
FIFO
AUTHENTICATION
INTERNAL
CLOCK
CD ESP
GNDA2
GNDA1
SPO
VC2
MDIN2
MDIN1
VCCA1
CLVS
VSS
MDSOUT
VDD
MDPOUT
GSCOR
EXCK
SBIN
VSS
SCOR
WFCK
VDD5V
XRCI
VDDS
C2PO
VDD
DBCK
BCLK
DDAT
MDAT
VSS
DLRC
LRCK
IFS0
IFS1
XRST
XTAL
VSS
XTL2
XTL1
D0
D1
D2
D3
D4
VDD
DFCT/LINK
D5
D6
VSS
D7
A0
VDD
A1
VDD5V
A2
A3
A4
A5
A6
A7
VSS
XWAIT
XRD
XWR
XCS
XINT0
XINT1
XHRS
HDB7
VSS
HDB8
HDB6
VDDS
HDB9
HDB5
HDBA
HDB4
VSS
HDBB
HDB3
VDD
HDBC
VDDS
HDB2
HDBD
HDB1
VSS
HDBE
HDB0
VDD
VDD
MA7
MA6
MA5
MA4
MA3
MA2
VSS
MA1
MA0
XRAS
MDB7
MDB6
MDB5
VDD5V
MDB4
VSS
MDB3
MDB2
MDB1
MDB0
VDD
XMWR
DASP
VDD
HCS1
HCS0
VSS
HA2
HA0
VDDS
XPDI
HA1
XS16
HINT
XHAC
VSS
REDY
VDD
XHRD
XHWR
VDDS
HDRQ
HDBF
FDO
PDHVCC
PDO
VCCA2
VCCA3
GNDA3
GNDA4
VCCA4
VCCA5
VCOIN
VCOR1
RFIN
RFDCC
DASYI
ASF2
ASF1
GNDA5
DASYO
VDD
APEO
VSS
GFS
MDBF
MDBE
MDBD
VDD5V
MDBC
MDBB
VDD
MDBA
VSS
MDB9
MDB8
XCAS
XMOE
MA11/MNT2
MA10/MNT1
MA9/MNT0
VSS
MA8
LPF2
VC1
LPF5
LPF1
62
SCD-C222ES
– AUDIO Board –
IC301-303
CXD9658N
MODE
CONTROL
PCM
INTERFACE
POWER
CONTROL
PCM
FILTER
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
DSD
INTERFACE
MUX
DSD
FILTER
MUX
MULTI-LEVEL
DELTA-SIGMA
MODULATOR
MULTI-LEVEL
D/A
CONVERTER
ANALOG
LOW-PASS
FILTER
11
12
DSDL
DSDR
PBCK
PDATA
PLRCK
DGND
VDD
VCC
VOUTL
VOUTR
AGND
VCOM
ZEROL/NA
ZEROR/ZEROA
MD
MC
MS
PSCK
DSCK
DBCK
IC509
CXD3068Q
DOUT
LRCK
PCMD
BCK
DVDD2
ASYE
MD2
EMPH
XTSL
DVSS2
XTAI
XTAO
SQSO
SQCK
SCSY
SBSO
EXCK
SOUT
SOCK
XOLT
SE
TE
VC
TES1
TEST1
DVSS1
FRDR
FFDR
TRDR
TFDR
SRDR
SFDR
DVDD1
FSTO
SSTP
MDP
LOCK
PWMI
FOK
DFCT
DIGITAL
CLV
PROCESSOR
OSC
DIGITAL
OUT
EFM
DEMODULATOR
32K
RAM
ERROR
CORRECTOR
D/A DIGITAL
INTERFACE
MIRR, DFCT,
FOK
DETECTOR
CPU
INTERFACE
SUBCODE
PROCESSOR
SERVO
AUTO
SEQUENCER
SERVO INTERFACE
DVDD0
XRST
MUTE
D
ATA
XLA
T
CLOK
SENS
SCLK
A
TSK
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
C4M
WDCK
DVSS0
COUT
MIRR
A
VDD0
IGEN
A
VSS0
ADIO
RFDC
CE
TE
A
VSS1
RF
AC
ASYI
ASYO
BIAS
A
VDD1
PCO
FILI
FILO
CL
TV
V16M
VCTL
VPCO
59 58
57 56 55 54 53 52
51 50 49 48
47 46 45 44 43 42 41
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
OPERA
TIONAL
AMPLIFIER &
ANALOG SWITCH
A/D
CONVER
TER
FOCUS
PWM
GENERATOR
TRACKING
PWM
GENERATOR
SLED
PWM
PWM
GENERATOR
FOCUS
SERVO
SERVO
DSP
TRACKING
SERVO
DSP
SLED
SERVO
DSP
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
60
63
SCD-C222ES
6-26.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC509 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
DVDD0
—
Power supply terminal (+3.3V) (digital system)
2
XRST
I
Reset signal input from the I/O expander (IC902) “L”: reset
3
MUTE
I
Muting on/off control signal input from the I/O expander (IC902) “H”: muting on
4
DATA
I
Serial data input from the CPU (IC901)
5
XLAT
I
Serial data latch pulse signal input from the CPU (IC901)
6
CLOK
I
Serial data transfer clock signal input from the CPU (IC901)
7
SENS
O
Internal status (SENSE) signal output to the CPU (IC901)
8
SCLK
I
SENSE serial data reading clock signal input from the CPU (IC901)
9
ATSK
I/O
Input/output terminal for anti-shock Not used (pull down)
10
WFCK
O
Write frame clock signal output to the CXD1882R (IC701)
11
RFCK
O
RFCK signal output terminal Not used (open)
12
XPCK
O
XPCK signal output terminal Not used (open)
13
GFS
O
Guard frame sync signal output to the CPU (IC901)
14
C2PO
O
C2 pointer signal output to the CXD1882R (IC701)
15
SCOR
O
Subcode sync (S0+S1) detection signal output to the CXD1882R (IC701) and CPU (IC901)
16
C4M
O
4.2336 MHz clock signal output terminal Not used (open)
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output to the CXD1882R (IC701)
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output to the CPU (IC901)
20
MIRR
O
Mirror signal output to the CPU (IC901)
21
DFCT
I/O
Defect signal input/output terminal Not used (pull up)
22
FOK
O
Focus OK signal output to the CPU (IC901)
23
PWMI
I
Spindle motor external control signal input terminal Not used (fixed at “L”)
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
25
MDP
O
Spindle motor (M3) servo drive signal output to the CXD1882R (IC701)
26
SSTP
I
Detection signal input from limit in switch (S1)
The optical pick-up is inner position when “H”
The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used (open)
28
DVDD1
—
Power supply terminal (+3.3V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output to the BA5938FP (IC502)
30
SRDR
O
Sled servo drive PWM signal (–) output to the BA5938FP (IC502)
31
TFDR
O
Tracking servo drive PWM signal (+) output to the BA5938FP (IC502)
32
TRDR
O
Tracking servo drive PWM signal (–) output to the BA5938FP (IC502)
33
FFDR
O
Focus servo drive PWM signal (+) output to the BA5938FP (IC502)
34
FRDR
O
Focus servo drive PWM signal (–) output to the BA5938FP (IC502)
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test (fixed at “L”)
37
TES1
I
Input terminal for the test (fixed at “L”)
38
VC
I
Middle point voltage (+1.65V) input from the NJM3403AV (IC004)
39
FE
I
Focus error signal input from the CXD1881R (IC001)
40
SE
I
Sled error signal input from the CXD1881R (IC001)
41
TE
I
Tracking error signal input from the CXD1881R (IC001)
42
CE
I
Middle point servo analog signal input from the NJM3403AV (IC004)
43
RFDC
I
RF signal input from the CXD1881R (IC001)
44
ADIO
O
Output terminal for the test Not used (open)
64
SCD-C222ES
Pin No.
Pin Name
I/O
Description
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+3.3V) (analog system)
48
ASYO
O
EFM full-swing output terminal
49
ASYI
I
Asymmetry comparator voltage input terminal
50
RFAC
I
EFM signal input from the CXD1881R (IC001)
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge pump output for master PLL
56
AVDD1
—
Power supply terminal (+3.3V) (analog system)
57
BIAS
I
Asymmetry circuit constant current input terminal
58
VCTL
I
VCO control voltage input terminal for the wideband EFM PLL Not used (fixed at “L”)
59
V16M
O
VCO oscillation output terminal for the wideband EFM PLL Not used (open)
60
VPCO
O
Charge pump output terminal for the wideband EFM PLL Not used (pull down)
61
DVDD2
—
Power supply terminal (+3.3V) (digital system)
62
ASYE
I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on
Not used (fixed at “H”)
Not used (fixed at “H”)
63
MD2
I
Digital out on/off control signal input from the CPU (IC901)
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
64
DOUT
O
Digital audio signal output to the DIGITAL (CD) OPTICAL OUT (IC309)
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the CXD1882R (IC701) and CXD9647R (IC803)
66
PCMD
O
Serial data output to the CXD1882R (IC701) and CXD9647R (IC803)
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the CXD1882R (IC701) and CXD9647R (IC803)
68
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used (open)
“H” is output when playback disc is emphasis on Not used (open)
69
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz (fixed at “H” in this set)
“L”: 16.9344 MHz, “H”: 33.8688MHz (fixed at “H” in this set)
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.8688 MHz)
72
XTAO
O
System clock output terminal (33.8688 MHz) Not used (open)
73
SOUT
O
Serial data output terminal Not used (open)
74
SOCK
O
Serial data reading clock signal output terminal Not used (open)
75
XOLT
O
Serial data latch pulse signal output terminal Not used (open)
76
SQSO
O
Subcode Q data output to the CPU (IC901)
77
SQCK
I
Subcode Q data reading clock signal input from the CPU (IC901)
78
SCSY
I
Input terminal for resynchronism of guard subcode sync (S0+S1) Not used (open)
79
SBSO
O
Subcode serial data output to the CXD1882R (IC701)
80
EXCK
I
Subcode serial data reading clock signal input to the CXD1882R (IC701)
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