Sony PMC-DR45 Service Manual ▷ View online
PMC-DR45
– 59 –
– 60 –
1
A
B
C
D
2
3
4
5
6
7
8
9
6-21. PRINTED WIRING BOARD — LINE SECTION — • Refer to page 34 for Note.
6-22. SCHEMATIC DIAGRAM — LINE SECTION — • Refer to page 68 for IC Block Diagram. • Refer to page 33 for Note.
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : CD PLAY
no mark : CD PLAY
(Page 38)
(Page 45)
(Page 40)
(Page 47)
PMC-DR45
– 61 –
– 62 –
1
A
B
C
D
E
F
G
H
I
J
2
3
4
5
6
7
8
9
10
6-23. PRINTED WIRING BOARDS — POWER SECTION — • Refer to page 34 for Note.
D901
F-2
D902
F-2
D903
F-3
D904
F-3
D905
C-1
D906
D-2
D907
D-2
D908
C-2
D909
D-2
D910
H-2
D911
H-2
D912
H-3
IC311
F-7
Q901
I-1
Q902
H-3
Q903
I-3
Q904
H-2
Q905
G-2
Q906
I-2
Q907
H-2
Q908
I-2
Q909
I-1
Q910
G-1
Q911
G-1
Q912
H-4
Q913
H-3
• Semiconductor
Location
Ref. No.
Location
(Page 46)
PMC-DR45
– 63 –
– 64 –
6-24. SCHEMATIC DIAGRAM — POWER SECTION — • Refer to page 33 for Note.
(Page 48)
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
no mark : FM
Note:
The components identi-
fied by mark
The components identi-
fied by mark
0
or dotted
line with mark
0
are criti-
cal for safety.
Replace only with part
number specified.
Replace only with part
number specified.
Note:
Les composants identifiés par
une marque
Les composants identifiés par
une marque
0
sont critiques
pour la sécurité.
Ne les remplacer que par une
piéce portant le numéro
spécifié.
Ne les remplacer que par une
piéce portant le numéro
spécifié.
– 65 –
– 66 –
1
2
3
4
8
9
10
11
12
7
18
19
20
21
22
23
24
17
16
15
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
6
VEE
VEE
VC
VEE
VCC
VCC
VREF
APC PD AMP
APC LD AMP
VC
VCC
+
–
–
5
VC
VC
VC
VCC
VEE
+
–
–
VC
+
–
–
VC
+
–
–
+
–
VC
+
–
–
RF EQ AMP
RF SUMMING AMP
VC
ERROR AMP
FOCUS
14
13
VEE
VC
VC
VC BUFFER
TRACKING
ERROR AMP
HOLD
AGCVTH
LD
PD
A
B
C
D
VEE
F
E
VC
VCC
LC/PD
LD ON
HOLD SW
RF BOT
RFTC
RF 1
RF 0
RFE
FE
TE
AGCCONT
(50%/30%
OFF)
(50%/30%
OFF)
28
27
26
+ –
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
INTERFACE
MUTE
LEVEL SHIFT
INTERFACE
F
R
R
F
R
F
INTERFACE
R
F
R
F
17
15
16
11
10
9
8
12
14
13
VCC
VREF
VCC
VCC
VCC
VCC
VREF
NC
SPIN
SFDR
SRDR
CAPS
GND
MUTE
VCC
SL
–
SL+
SP
–
SP+
VREFOUT
FFDR
FRDR
CAP1
TFDR
TRDR
CAP2
GND
VREFIN
VCC
T+
T
–
F–
F+
IC1 TA2149N
6-25. IC BLOCK DIAGRAMS
IC2 LC72137M-TLM
IC701 CXA2568M
IC703 BA5974FP
GND1
3
2
1
IF REQ
AM
MIX
FM RF-IN
AM LOW CUT
5
4
MIX OUT
VCC2
AF IF-IN
8
7
6
FM IF-IN
GND2
10
9
AGC
QUAD
12
11
R-OUT
L-OUT
FM RF-OUT
22
23
24
20
21
17
18
19
15
16
13
14
AM RF-IN
VCC1
FM OSC
ST-IND
OSC-OUT
AM OSC
IF-OUT
LPF2/MO-ST
MPX- IN
DET-OUT
LPF1/BAND
FM
MIX
FM
OSC
LEVEL
DET
AM
DET
MUTE
FM
DET
ST/MO
FM/AM
AM
OSC
AGC
SW
ST
1/8
BUFF
BUFF
DIVIDE
DECODE
VCO
IF BUFF
AF BUFF
AF
FM RF
AM IF
FM IF
1/1 OR
1/16
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
19
20
UNLOCK
DETECTOR
POWER ON
RESET
UNIVERSAL
COUNTER
CCB
I/F
CE
DI
CL
DO
XOUT
LP-OUT
XIN
LP-IN
PD
VSS
VDD
MO/ST
FM IN
AM IN
MUTE
MW/LW
BAND
ST-IND
BAND
IF IN
PHASE
DETECTOR
CHARGE
PUMP
REFERENCE
DIVIDER
SWALLOW
COUNTER
1/16,1/17
4BITS
12BITS
PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
1/2
17
18
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