Sony PMC-222V Service Manual ▷ View online
— 63 —
5-11.
IC PIN FUNCTION DESCRIPTION
CONTROL BOARD IC801 MSM65354-408GS-BK4 (SYSTEM CONTROL, LCD DRIVE)
Pin No.
1 to 4
5 to 36
37
38 to 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
O
O
—
I
I
I
I
—
—
—
O
O
I
O
O
I
O
O
O
O
O
O
O
O
O
—
I
O
I
O
I
O
O
—
—
I
I
I
I
I
I
I
Description
LCD common output
LCD Segment output
Analog ground
Key input
9k/10k select input
Volume initial setting input (Fixed at “L”)
Input for power check
Connected to ground
AD reference voltage input
Analog power supply (+5V)
PLL chip enable output
PLL data output
PLL data input
PLL serial clock
EEPROM chip select
EEPROM read/wired or to MD
EEPROM write/wired or to MD
EEPROM R/W clock output
Analog SW control
Analog SW, power supply control
Power supply control
Power on/off control output
CD/VCD system reset
CD DSP command latch
CD DSP command data
CD DSP command clock
Not used (OPEN)
Subcode serial data input
Subcode read clock output
Remote control signal input
DBB on/off control output
VDO acknowledgement reading
I
2
CBUS serial data output
I
2
CBUS serial clock output
Digital power supply (+5V)
Not used
FM stereo indicator control input
CD SENS signal input
INT-1 input/both edge detect
MD Recording switch input
MD head position switch input
Hard stop mode input
CD subcode read enable input
Pin Name
COM1 to COM4
SEG0 to SEG31
A-GND
KEY1 to KEY4
9/10
VOL-INI
VCHK
NC (GND)
VRH
AVDD
RCE
RDO
RDI
RCK
MCS
MDI
MDO
MSK
TA
TU
CD
PCNT
XRST
CLT
CDO
CCK
NC (OPEN)
SQSO
SQCK
RMC
DBB
ACKW
VDO
VCK
VDD
NC (GND)
STID
SENS
DOP
REC
PLAY
H STOP
SCOR
— 64 —
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98 to 100
I/O
O
I
—
I
O
—
O
O
I/O
O
O
I
O
I
—
—
—
Description
Main clock output (4.19MHz)
Main clock input (4.19MHz)
Digital ground
32.678kHz OSC input
32.678kHz OSC output
Not used (OPEN)
CD/VCD sound muting
Tuner block muting
Audio output muting
CD/VCD CC-CBUS Line
CD/VCD CC-CBUS Line
CD/VCD CC-CBUS Line
CD/VCD CC-CBUS Line
Reset input
Connected to ground
Not used (OPEN)
Bias power supply for LCD drive
Bias power supply for LCD drive
Pin Name
OSC1
OSC0
D-GND
XTI
XTO
NC (GND)
C MUT
B MUT
A MUT
CCE
BUO
BUI
BUCK
RST
NC (GND)
NC (OPEN)
VDDL
VDD1 to VDD3
— 65 —
Pin No.
1
2
3
4
5
6 to 13
14
15
16
17
18
19
20
21
22 to 29
30
31 to 38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55 to 57
58
59
60
61
62
I/O
I/O
—
I
I
I
I
I
I
—
I/O
I/O
—
I
I
I
—
I
—
O
O
O
I
I
—
—
—
O
—
—
—
—
—
I
I
I
—
I
I
I
Description
Charge pump output/VCO input
Digital ground
Video mode select control. When 0, NTSC mode, when 1, PAL mode.
Video sync mode select control. When 0, internal sync mode, when 1, external sync mode.
Reset input
B data input
Test input
Pixel clock input
Power supply for digital circuit
Horizontal sync. signal input/output
Vertical sync. signal input/output
Digital ground
Input format select
Built-in trap filter control
G data or Y data input
Power supply for digital circuit
R data or CbCr data input
Digital ground
Clock out
Field discri. signal out. Odd: “H”, Even: L out.
Clock for OSD IC output
Video data input control
Sleep mode select “H”: Active
Power supply for analog circuit
Open
Open
Analog video signal out
Connected to resistor for full scale output current value setting
Open
Connected to de-coupling capacitor for phase correction
Analog ground
Analog ground
CDG/PAL4fsc mode select signal
OSD color select
OSD, background picture control
Digital ground
CDG mode select control
PAL60 mode select control
Two times pixel rate frequency input
Pin Name
VCOIN
GND
PALMODE
MASTERB
RESETB
B7 to B0
TESTI0
PXCLK
VCC
HSYNCB
VSYNCB
GND
FORM
TRAPFEN
G7 to G0
VCC
R7 to R0
GND
CLKOUT
FLDOUT
OSDCLK
DICNT
SLEEP
AVCC
NC
NC
VIDEO
IREF
NC
COMP
AGND
AGND
PAL4FSC
OSD2 to OSD0
VSW
GND
CDGMODE
PAL60
CLKMODE
VCD BOARD U1006 RL5C293 (DIGITAL RGB TO NTSC/PAL ENCODER)
— 66 —
Pin No.
1
2
3 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22 to 29
30
31
32
33 to 42
43
44 to 48
49
50
51
52 to 59
60
61
62 to 64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83 to 90
91 to 95
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
O
O
O
O
I/O
O
O
O
O
I
O
O
I
I
O
I
O
I
I
I
I
O
I
O
Description
P1.0 of 8051
Digital VCC
P1.1 to P1.7 of 8051
Digital ground
X’tal input
X’tal output
RxD of 8051
TxD of 8051
INT0 of 8051
INT1 of 8051
T0 of 8051
T1 of 8051
WR of 8051
RD of 8051
PSEN of 8051
Data bus bit 0 to 7 of 8051
Digital VCC
Digital ground
Test pin, Normally pull low
Address bus bit 0 to 9 of 8051
Address bus bit 10 of 8051, SRAM chip enable
Address bus bit 11 to 15 of 8051
Address latch enable
Test data latch signal
Digital ground
CL480 host data interface
CL480 host data strobe signal
CL480 host data read/write signal
CL480 host address interface
Extention I/O Port enable signal
PLL clock output mode 1: 16.9344MHz 0: 11.2896MHz
Reset signal output. Its output is controlled by/PWRCTLI signal.
Analog ground
PLL charge pump output
PLL VCO input
Analog VDD
PLL test pin, It should be connected to SYSRST pin for normal operation.
PLL clock output, Its output is controlled by/PWRCTLI signal.
PLL clock input
Power-on reset signal output. It’s output is controlled by/PWRCTLI
Power-On reset signal input
Audio switch signal
NTSC/PAL indicator input, internal pull-down
Board test mode selection input, internal pull-up
Digital VCC
Digital ground
Mute signal output
Key scan matrix column 7 to 0
Key scan matrix row 7 to 3
Pin Name
P1.0
VCC
P1.1 to P1.7
GND
X1
X2
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PSEN
BD0 to BD7
VCC
GND
CPUTST
A0 to A9
A10/SRAM
A11 to A15
ALE
KEYWR
GND
HD7 to HD0
DS
R/W
HSEL2 to HSEL0
ENH
CLK-HIGH
RESET
AGND
CPO
VCI
AVDD
PLL/PD
DA-XCLK
CD-BCK
SYSRST
480RST
AUD-SW
NTSC
TEST
VCC
GND
MUTE
COL7 to COL0
ROW7 to ROW3
VCD BOARD U1008 VIS2088 (VCD SYSTEM CONTROL)
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