Sony PCM-M1 Service Manual ▷ View online
INSTRUCTION
REGISTER
INSTRUCTION
DECODE.
CONTROL
AND
CLOCK
GENERATION
DATA
REGISTER
R/W AMPS
AND
AUTO
ERASE
EEPROM
2048BIT
(128x16)
ADD.
BUFFERS
DECODER
VPP SW
VPP
GENERATOR
V REF
7
RDY/BUSY
4
DO
8
3
1
2
6
5 GND
RESET
SK
CS
DI
Vcc
3
7
14
16
16
14
8BIT
LATCH
8BIT
D/A CONV.
R-2R
D0
D7
8BIT
LATCH
8BIT
D/A CONV.
R-2R
D0
D7
12BIT SHIFT REGISTER
ADDRESS
DECODER
14
13
9
8
16
15 2 7 10
1
11
12
DO
LD
DI
CLK
VCC
VDD
GND
AO1 AO8
VSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11
8
1
8
1
8
8
.
.
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
17
18
19
20
21
22
23
24
SCP
TC
V REF
RT
SB
VAO 1
VI 1–
VI 1+
RB 1
VC 1
CB1 B
CB1 A
VCC
CT 1
CT 2
GND
DTC
VAO 2
VI 2–
VI 2+
VC 2
RB 2
CB2 B
CB2 A
TRIANGLE
GENERATOR
REGULATOR
+
+
+
+
6
12
VEE
GND
11
9
8
10
2
4
1
3
5
Vcc
1ch
1ch
A
B
1ch OUT
1KEY
2ch
2ch
A
B
2ch OUT
2Key
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
COMMAND/CONTROL
UNIT
b15
b0
16-BIT
I/O SHIFT
REGISTER
I/O SHIFT
REGISTER
65-TO-1
MULTIPLEXER
MULTIPLEXER
65-TO-1
MULTIPLEXER
MULTIPLEXER
POS64
POS0
POS64
POS0
GND
COUT
CLK
DIN
CS
ZCEN
MODE
W0
L0
H0
VCC
VU(UC1)
VD(DC1)
B0(UC0)
B1(DC0)
MUTE
AGND
H1
L1
W1
IC508 AK6420HM-E2
IC518 MB88347PFV
IC503 MB3796
IC310 TK15325MT-L
IC306 DS1802E
– 32 –
1
2
3
4
5
6
7
8
9
10
12
11
24
23
22
21
20
19
18
17
16
15
13
14
ROTOR
POSITION
DETECT
OUTPUT
DRIVE
BUFFER
TIMING
CONTROL
START
CONTROL
SOFT
SWITCHING
DRIVE
OVER HEAT PROTECT
STBY
STAT
GND
COM
W IN
V IN
U IN
VCC
3
VS
U
I COM
V
BRAKE
FG
CSLP1
CSLP2
IB
IB SET
IB S
VCC 1
VS
W
I COM
EXOR
PFD
1
14
2
LOGIC
VDD
SELECT
VCO
OUT
OUT
FIN-A
FIN-B
PFD
OUT
OUT
LOGIC
GND
VCO
VDD
VDD
R VIAS
VCO
IN
VCO
GND
GND
VCO
INHIBIT
PFD
INHIBIT
NC
3
4
13
5
6
7
8
12
11
10
9
1/2 DIVIDER
VCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W OUT
VS
VCC 2
VCC 1
TRC
FILTER
FC
VH
AGC
FG IN +
FG IN –
FG OUT
GND
ST.BY
(H.ACTIVE)
(H.ACTIVE)
FRC
W IN 2
W IN 1
V IN 2
V IN 1
U IN 2
U IN 1
RF
U OUT
V OUT
MATRIX
HALL AMP
ACC
TSD
FORWARD/REVERSE
REFERENCE
VOLTAGE
VCC
IC502 CXA8022N
IC511 TLC29321
IC504 LB1882V
– 33 –
— 45 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
O
O
—
O
O
O
O
O
O
I
O
I
—
I
O
O
I
O
O
O
I
I
O
O
O
O
O
O
O
I
O
I
O
I
I
I
I
—
O
O
O
I
O
I
I
I
O
O
I
I
Description
+5v
External RAM address input.
External RAM address input.
External RAM address input.
External RAM address input.
External RAM address input.
External RAM write enable signal output.
External RAM output enable signal output.
External addressing enable signal output.
Test input, fixed to “L”.
X’tal oscillator circuit -1 output (not used).
X’tal oscillator circuit -1 input (not used).
GND.
Reset input. Reset at “L”.
System clock output (Frequency is 4.9152 MHz when SELC = “L”, 8.192 MHz when SELC = “H”).
* 1 control byte (1). Q code decode (music interval detection) output when bit 1 = “L”, BCK clock output from
RX-PLL when bit 1 = “H”).
ATF sync signal input.
Channel clock (fch) output.
Signal output with duty 50 at SBSY rate.
Control byte (1). Data transfer monitoring signal output with microprocessor when bit 1 = “L” (Transfer is
enabled at “L”), f256 clock output from RX-PLL when bit 1 = “H”).
Clock input for data transfer with microprocessor.
Serial data input from microprocessor.
Serial data output to microprocessor.
Frame cycle signal output for data transfer with microprocessor.
PLL clock divided-by-5880 output.
9.8304 MHz output when SELC = “L”, 12.288 MHz output when SELC = “H”.
Mute input, mute at “H”. REC monitor sound is not muted.
Mute monitor. The mute status is indicated by “H”.
RXPLL lock monitor signal output. Indicates the RXPLL is locked.
Playback RF signal control (RF signal is valid at “L”, RF signal is invalid at “H”.)
Monitor signal indicating result of CI check which supports RF.
Oscillating frequency selection signal input.
Control byte (1). RFPLL clock output when bit 1 = “L”, f128 clock output from RX-PLL when bit 1 = “H”).
Test terminal, fixed to “L”.
Playback RF signal input.
Chip select input for data transfer with microprocessor. Transfer enable at “L”.
RF switching pulse. “A” track at “L”. “B” track at “H”.
GND.
ATF pilot signal of wiring signal/identification signal output. Pilot signal at “H”.
REC/PB discriminating signal input. REC state at “H”.
Wiring signal output.
Test terminal, fixed to “L”.
Phase comparator output for RXPLL.
Oscillating frequency selection signal input.
Mute input, mute at “H”. REC monitor sound is also muted.
External VCO clock input of RXPLL. (512 fs reference).
Phase comparator signal output for RXPLL. (2 fs generated from PLL clock).
Phase comparator signal output for RXPLL. (2 fs of rxx sync detection signal).
Master mode/slave mode select. Master at “H”.
Digital interface signal input.
Pin Name
Vpp
A10
A11
A12
A13
A14
XWE
WOE
XEAN
TST1
XT10
XT11
Vss
XRST
CLKO
MINT
ATSY
MCLK
DREF
SBPM
EXCK
SDSI
SDSO
SBSY
RFPL
CCLK
MUTE
MUTM
UNLK
RFCT
SYMN
SELB
PLCK
TST2
RFDT
XCS
SWP
Vss
PIPC
REPB
REDT
TST4
PDO
SELC
MUTA
PLCO
PLVR
PLRF
MSSL
RX
4-7.
IC PIN FUNCTION
• IC506 CXD2607BR
— 46 —
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
—
O
I
I/O
I/O
I/O
O
O
I
I
O
I
—
O
I
I
O
O
O
I/O
O
O
I/O
I
O
I
O
I
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
0
0
0
0
0
0
0
0
0
Description
+5 v.
Digital interface signal output.
Oscillating frequency selection signal input.
External sync signal input/output. Normally connected to EXSN.
External sync signal input/output. Normally connected to EXSY.
128 fs signal/256 fs signal during double speed input/output.
256 fs signal/512 fs signal during double speed input/output.
512 fs signal output.
LSB/MSB first of ADDT, ADDI and ADDN serial data select input. LSB first at “H”.
LSB/MSB first of DADT and DADO serial data select input. LSB first at “H”.
X’tal oscillator circuit-2 output. 22.579 MHz.
X’tal oscillator circuit-2 input.
GND.
X’tal oscillator circuit-3 output. 24.576 MHz.
X’tal oscillator circuit-3 input.
F128, BCK and LRCK input;output select input. Output at “H”.
Inverted signal of LR02.
Control byte (1). 16BCK delay signal of LRCK when bit 1 = “L”, LRCK clock output from RX-PLL when bit 1
= “H”.
15BCK delay signal of LRCK.
Fs signal/2 fs signal during double speed input/output.
2 fs signal/4 fs signal during double speed input/output.
Inverted signal output of BCK.
64 fs signal/128 fs signal during double speed input/output.
AD serial data input.
DA serial data input.
Audio data input for digital output. (Connected to DADT normally).
Digital in audio data output.
Audio data input for DIGITAL IN. (Connected to ADDI normally).
Validity flag data input for digital out. (Connected to ERRF normally).
Error data plug/data output of DADT data. Error data at “H”.
Indicates that the error correction status monitor data is being output to D7 to D0 at “H”.
External RAM data input/output (MSB).
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
GND.
External RAM data input/output.
External RAM data input/output. (LSB).
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM data input/output.
External RAM address output.
External RAM address output.
Pin Name
Vpp
TX
SELA
EXSY
EXSN
F128
F256
F512
ADLF
DALF
XT2O
XT2I
Vss
XT30
XT31
PSEN
LR03
LR02
LR01
LRCK
WCK
XBCK
BCK
ADDT
DADT
DADO
ADDI
ADDN
ERRI
ERRF
MNTG
D7
D6
D5
D4
D3
D2
Vss
D1
D0
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
Click on the first or last page to see other PCM-M1 service manuals if exist.