Sony NW-S202 / NW-S202F / NW-S203F / NW-S205F Service Manual ▷ View online
NW-S202/S202F/S203F/S205F
9
3-7. CHASSIS
3-8. HEADPHONE BOARD
1
battery (A) assy
(lithium ion battery)
5
self tap screw
sheet
(headphone jack)
2
bracket USB
3
copper sheet
(plate PWB)
6
Push the
battery holder.
battery holder
7
chassis assy
4
HEADPHONE board
(ground portion)
chassis assy
Note: Sheet (headphone jack) cannot
be re-used.
Please replace to brand-new parts once
sheets (headphone jack) are removed.
sheet (headphone jack)
1
Turn over the HEADPHONE board in the direction of arrow A.
A
2
claw
3
HP holder
8
mini jack (headphone) (J901)
9
HEADPHONE board
7
Remove three solders.
4
O ring (HP) assy
6
battery holder
5
spacer (FPC stopper)
adhesive sheet (FPC)
Note 1: Please work noting that the HEADPHONE board is damaged.
Note 2: Adhesive sheet (FPC) cannot be re-used. Please replace to
brand-new part once adhesive sheet (FPC) is removed.
Note 3: Sheet (headphone jack) cannot be re-used.
Please replace to brand-new part once
sheet (headphone jack) is removed.
NW-S202/S202F/S203F/S205F
10
SECTION 4
TEST MODE
1.
SETTING THE TEST MODE
Supply power to the set, While pressing the
B x key, press the
key as following order.
[VOL +] → [VOL +] → [VOL -] → [VOL -] → [VOL +] → [VOL -]
→ [VOL +] → [VOL -] → [DISP] → [DISP]
[VOL +] → [VOL +] → [VOL -] → [VOL -] → [VOL +] → [VOL -]
→ [VOL +] → [VOL -] → [DISP] → [DISP]
2.
OPERATION OF THE TEST MODE
The item is selected by pressing
[VOL +] [VOL -] key, and the item
is decided by pressing
B x key.
Released from the item by pressing
[DISP] key.
The item of “Hall Calib.” and “Gsensor” is not released if it
doesn't reboot.)
2-1. Hall Calib.
Jog shuttle (Hall IC) calibration mode.
Refer to supplement-2 for details of this item.
2-2. Gsensor
G Sensor Calibration mode.
Already because this function has been adjusted, this mode has
not used in service.
2-3. ALL Key Check
When all keys and the shuttle switches are correctly input, the set
is reboots.
2-4. Set CHG Current
The charge currents are set to either of 500 mA/100 mA.
2-5.
CHG Start/Stop
Start/stop of the charge is set.
2-6. Information
The set information display mode.
Example of display:
0.85.00.10 [JP]
TUNER:YES 1GB
Detailed version of
F/W
F/W
Region
TUNER YES/NO
FLASH memory size
2-7. HallCalibData
Mode that displays information set at calibration of hall.
Display the X/Y value of
[HOLD]/center position/[FOLDER +]/
[FOLDER -] positions after 45degree transformation.
This is used in designing group only.
This is used in designing group only.
3.
METHOD OF RESETTING THE SET
The set resets to keep about 7 seconds with
[DISP] and B x key
pressed at the same time.
The display of “ACCESS” appears when reset and the set boots.
The set cannot be reset if it is not charged. Reset the set after it
charges it by way of the USB cable.
Please take off from the key if “ACCESS” message does not
appear.
Ver. 1.3
NW-S202/S202F/S203F/S205F
11
11
NW-S202/S202F/S203F/S205F
SECTION 5
DIAGRAMS
5-1. BLOCK DIAGRAM
CN101
(USB CONNECTOR)
VBUS
D-
D-
GND
D+
DM
DP
DP
X101
12MHz
TX
TEX
HPOUTL
HPOUTR
X102
45.1584MHz
XTAL
EXTAL
J901
(HEADPHONE)
LITHIUM ION
BATTERY
3.7V 500mA
POWER CONTROL
IC601
3 AXIS ACCELEROMETER
IC801
D601
NCLE/GPIOC8 9
I/O1
I/O8
I/O8
NAND FLASH ROM
IC1301
NAD0/GPIOC0
NAD7/GPIOC7
NAD7/GPIOC7
CLE
16
NALE/GPIOC9 10
ALE
17
NWE/GPIOC15 16
XWE
18
NWP/GPIOC16 17
XWP
19
NRB0/GPIOC17 18
R/B1
7
NRE/GPIOC14 15
XRE
8
NCE0/GPIOC10 11
XCE1
9
29
32
41
32
41
.
1
8
8
8
44
RE/GPIOA26 236
204 − 211,
222 − 229
31, 32,
37 − 41,
44, 45,
48, 49,
51 − 53,
55, 56
DQ0
DQ15
32MB FLASH ROM & 4MB SRAM
IC201
161 − 176,
195 − 199
A1 − A21
D0 − D4,
D5/GPIOA9 − D15/GPIOA19
1,
5 − 8,
12 − 17,
19 − 21,
23 − 27,
29, 34
A0
A20
ORGANIC EL
INDICATOR
MODULE
EL401
XOE
36
CS0/GPIOA21 231
XCE1F
35
RST 265
ARST 113
XRSTF
10
WE/GPIOA27 237
XWE
4
CS1/GPIOA22 232
XCE1S
43
UB/GPIOA29 239
XUB
9
LB/GPIOA28 238
XLB
VDD IO +2.8V
2
CS2/GPIOA23 233
SDDAT3/INT5/GPIOF4 91
SDDAT2/INT4/GPIOF3 90
SDDAT2/INT4/GPIOF3 90
SDDAT1/DACK/INT3/GPIOF2
MSDIO2/GPIOE3
MSDIO3/GPIOE4
MSDIO1/GPIOE2
MSDIO3/GPIOE4
MSDIO1/GPIOE2
RST2OUT
VBUS/GPIOD0
VBUS/GPIOD0
WAIT/GPIOA20
AN7
USB_IN2
USB_IN1
VDD AD +2.0V
VDD CORE +1.2V
VDD CORE +1.2V
VDD IO +2.8V
BAT1
BAT2
BAT2
OUT_AD 17
28
LX_CORE
VDD USB +3.3V
OUT_USB3.3 35
VDD UNREG
VDD NAND +2.8V
24
LX_IO
OUT_CORE
USB_H/L
XCHG_STAT
XCHG_EN
IU3
EN
USB_POK
BATTERY
VOLTAGE
DETECT
Q601,602
B+ SWITCH
Q604
CHARGE
CONTROL
Q605
SYSTEM CONTROLLER,
NAND FLASH INTERFACE,
USB INTERFACE,
A/D, D/A CONVERTER,
SERIAL INTERFACE
IC101
GPION0/INT8
AN0
S502, 503
GPION2/INT10
GPION3/INT11
WAKE UP
DETECT
Q501, 502
36
33
AOUTL
AOUTR 73
72
TUNER
IC2702
AOUT_R
5
AOUT_L
6
DA
7
LA
8
CL
9
STO
ANT
13
2
1
VCC
10
X1
VDD IO +2.8V
SIO/GPIOG1
SCK0 134
132
CS4/GPIOA25 235
SCS0/GPIOG2
SO0/GPIOG0 133
135
MICINL
MICINR 186
183
HALL ELEMENT DRIVER
IC901
SI
7
SO
5
SK
8
CS
10
MCLK
11
INT
HE1P
6
15
HE1N 16
STBYB 10
AX 5
AY 4
AY 4
AZ 3
GPION1/INT9 39
RSTN
12
SCL/GPIOK0 51
136
88
138
87
248
HALL
X901
HE2P 1
HE2N 20
HALL
X902
HE3P 14
HE3N 13
HALL
X903
HE4P 2
HE4N 3
HALL
X904
REAL TIME
CLOCK
X801
+2.7V
REGULATOR
IC2701
SI1/GPIOH1
137
SO1/GPIOH0
246
INTA
SCK1
SDDAT0/DREQ/INT2/GPIOF1
OSCIN
SDCMD/INT1/GPIOF0
9
8
10
3
6
DATA
CLK
CE0
CLK
CE0
FOUT
/TIRQ
/TIRQ
4 /AIRQ
8
21
21
16
8
16
DRIVE
Q401
126
125
118
125
118
119
115
115
116
38
AN2
79
AN3
80
HPINL
66
HPINR
68
AN4
81
T1/GPIOL1
54
CRST1A
VOLTAGE
DETECT
IC902
RESET SWITCH
IC901
259
GATE
258
DRAIN
252
VDD RTC +2.8V
RTCREGO
219
T3/GPIOL3
56
77
4
3
7
8
8
26
2
9
9
10
20
30
40
40
89
84
102
103
101
103
101
29
127
230
: AUDIO
• SIGNAL PATH
S504
DISP
VOL +/-
S501
B x
HOME
40
41
GATE
Q2701
(S202F/S203F/S205F)
NW-S202/S202F/S203F/S205F
12
12
NW-S202/S202F/S203F/S205F
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
For Printed Wiring Boards.
Note:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
• f : internal component.
•
• Y : parts extracted from the conductor side.
• f : internal component.
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
• MAIN board is multi-layer printed board.
However, the patterns of intermediate-layer have not been
However, the patterns of intermediate-layer have not been
included in diagram.
• Lead Layouts
For Schematic Diagrams.
Note:
• All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics and
50 WV or less are not indicated except for electrolytics and
tantalums.
• All resistors are in Ω and 1/4 Ω or less unless otherwise
specified.
• f : internal component.
• C : panel designation.
• C : panel designation.
• A : B+ Line.
• Power voltage is dc 3.7 V and fed with regulated dc power
• Power voltage is dc 3.7 V and fed with regulated dc power
supply from CN601 pin 1 and pin 2 on the MAIN board.
• Voltages are dc with respect to ground under no-signal
conditions.
no mark: PLAYBACK
• Voltages are taken with a VOM (Input impedance 10 MΩ).
• Voltage variations may be noted due to normal production
• Voltages are taken with a VOM (Input impedance 10 MΩ).
• Voltage variations may be noted due to normal production
tolerances.
• Signal path.
F
F
: AUDIO
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that of conventional IC.
from that of conventional IC.
* Replacement of IC101 and IC201 on the MAIN board
used in this set requires a special tool.
* Replacement of IC101 and IC201 on the MAIN board
used in this set requires a special tool.
Caution:
Pattern face side: Parts on the pattern face side seen from
(Conductor Side) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Component Side) the parts face are indicated.
(Conductor Side) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Component Side) the parts face are indicated.
Caution:
Pattern face side: Parts on the pattern face side seen from
(Side B)
(Side B)
the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Side A)
(Side A)
the parts face are indicated.
surface
Lead layout of conventional IC
CSP (chip size package)
• IC Block Diagrams
– MAIN Board –
– MAIN Board –
IC201 S71PL032J04BFWOBOB
1
A7
32 DQ6
33 NC
34 A16
35 XCE1F
36 XOE
37 DQ9
38 DQ3
39 DQ4
40 DQ13
41 DQ15
42 NC
31 DQ1
30 VSS
30 VSS
29 A0
SECTOR
SWITCHES
INPUT/OUTPUT
BUFFERS
ERASE VOLTAGE
GENERATOR
2
XLB
3
XWP/ACC
4
XWE
5
A8
6
A11
7
A3
8
A6
9
XUB
10
XRSTF
11
CE2S
12
A19
13
A12
14
A15
48
DQ12
49
DQ7
50
VSS
51
DQ8
52
DQ2
53
DQ1
1
54
NC
55
DQ5
56
DQ14
47
VCCS
46
VCCF
45
DQ10
44
DQ0
43
XCE1S
15
A2
16
A5
17
A18
18
RY
/XBY
19
A20
20
A9
21
A13
22
NC
23
A1
24
A4
25
A17
26
A10
27
A14
28
NC
DATA LATCH
Y-GATING
CELL MATRIX
Y-DECODER
X-DECODER
CHIP ENABLE
OUTPUT ENABLE
LOGIC
VIO
STATE
CONTROL
COMMAND
REGISTER
TIMER
VCC
DETECTER
PGM VOLTAGE
GENERATOR
ADDRESS LA
TCH
1
USB_SUS
22 IU4
23 PG_IO
24 LX_IO
25 IN_IO
26 OUT_CORE
27 IN_CORE
28 LX_CORE
29 PG_AORE
30 EN
21 OUT_IO
USB POWER
MANAGEMENT
2
USB_H/L
3
USB_IN1
4
USB_IN2
5
SYS1
6
SYS2
7
BAT1
8
BAT2
9
XCHG_STAT
10
XCHG_EN
33
IU6
34
IN_USB3.3
35
OUT_USB3.3
36
VL
37
IU7
38
IU8
39
IU9
40
USB_POK
41
SHEELD
32
XCHG_FL
T
31
IU5
11
THM
12
CHG_ISET
13
CT
14
GND
15
IU1
16
IN_AD
17
OUT_AD
18
IU2
19
BP
20
IU3
CORE
STEP-DOWN
REGULATOR
I/O
STEP-DOWN
REGULATOR
REF
1MHz OSC
LI+BATTERY
CHARGER
AND
SYS LOAD SWITCH
USB LDO 3.3V
REGURATOR
REG5
3.3V
A/D LDO 2.0V
REGURATOR
SEQUENCER
(FIGURE 7)
INPUT LIMITER
AND
CHARGER THERMAL
REGULATION
THERMAL-OVERLOAD
PROTECTION ABOVE TJ=+165 C
PWM
IC601 MAX8670A
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