Sony NW-MS7 Service Manual ▷ View online
– 17 –
Pin No.
Pin Name
I/O
Pin Description
66
VCC
—
Power supply terminal
67
VSS
—
Ground
68
PD31 F_SO
I
EEPROM serial data signal input terminal
69
PD30 F_SI
O
EEPROM serial data signal output terminal
70
PD29 F_CLK
O
EEPROM clock signal output terminal
71
PD28 U_XRST
O
USB reset signal output terminal
72
PD27 G_XRST
O
ATRAC3 IC reset signal output terminal
73
PD26 F_RST
O
EEPROM reset signal output terminal
74
PD25
O
Output port terminal Not used. (Open)
75
VSS
—
Ground
76
PD24 LCD_XRST
O
LCD reset signal output terminal
77
SCK1
O
System clock signal output terminal Not used. (Open)
78
PD22 LCD_CLK
O
LCD clock signal output terminal
79
VCC
—
Power supply terminal
80
PD21 DA_XRST
O
DA reset signal output terminal
81
PD20 FWE_CTRL
O
Flash write enable control signal output terminal
82
VSS
—
Ground
83
VCC
—
Power supply terminal
84
PD19 HP_MUTING
O
Headphone mutting signal output terminal
85
PD18 HP_BEEP
O
Headphone beep signal output terminal
86
VSS
—
Ground
87
PD17 WKUP_MSK
O
Wake up maskable signal output terminal
88
PD16 S_XRST
O
MG IC reset signal output terminal
89 – 92
D15 – D12
I/O
Data bus signal input/output terminal
93
VCC
—
Power supply terminal
94
D11
I/O
Data bus signal input/output terminal
95
VSS
—
Ground
96 – 102
D10 – D4
I/O
Data bus signal input/output terminal
103
VSS
—
Ground
104
VCC
—
Power supply terminal
105 – 108
D3 – D0
I/O
Data bus signal input/output terminal
109
VSS
—
Ground
110, 111
MD0, MD1
I
Mode setting input terminal
112
VCC
—
Power supply terminal
113
EXTAL
I
External clock signal input terminal
114
VSS
—
Ground
115
XTAL
O
Crystal signal output terminal
116
VCC
—
Power supply terminal
117, 118
MD2, MD3
I
Mode setting input terminal
119
FWE
I
Flash write enable signal input terminal
120
NMI
I
Nonmaskable interruption signal input terminal
121
XRES
I
Power on reset signal input terminal
122
VSS
—
Ground
123
CKIO
I/O
System clock signal input/output terminal Not used. (Open)
124
VCC
—
Power supply terminal
125
XHSTBY
I
Hardware standby signal input terminal
126
XWDTOVF
O
Watch dog timer over flow signal output terminal Not used. (Open)
127, 128
MD4, MD5
I
Mode setting input terminal
129
PLLVSS
I
PLL ground
130, 131
PLLCAP1, 2
I
PLL capacitor input terminal
132
PLLVCC
I
PLL power supply terminal
133
RXD2 ST_DO
I
ST Receive data signal input terminal RXD2: Not used.
134
VSS
—
Ground
– 18 –
Pin No.
Pin Name
I/O
Pin Description
135
XTAL32
O
Sub clock signal output terminal Not used. (Open)
136
EXTAL32
I
Sub clock signal input terminal
137
VCC
—
Power supply terminal
138
TXD2 ST_DI
O
ST transceiver data signal output terminal TXD2: Not used.
139
SCK2
O
System clock signal output terminal Not used. (Open)
140
VSS
—
Ground
141
CK
O
System clock signal output terminal
142
VCC
—
Power supply terminal
143
VSS
—
Ground
144
PE12 DA_ML
O
DA latch signal output terminal
145
PE13 DA_MC
O
DA clock signal output terminal
146
XIRQ6
I
Interruption request signal input terminal Not used. (Open)
147
PE15 DA_MD
O
DA data signal output terminal
148
XIRQ0 S_XIRQ
I
MG IC Interruption request signal input terminal
149
PE17 HP_BBON
O
Headphone bus boost ON signal output terminal
150
PE18 U_PWR
O
USB power signal output terminal
151
XIRQ3 MS_EJ
I
Memory stick eject signal input terminal
152
VSS
—
Ground
153
XIRQ4
I
Interruption request signal input terminal Not used. (Open)
154
XIRQ5
I
Interruption request signal input terminal Not used. (Open)
155
PE22 LCD_BL
I
LCD back light signal input terminal
156
XIRQ7 U_XIRQ
I
USB interruption request signal input terminal
157
U_XDACK
O
USB DMAC transfer strobe signal output terminal
158
PF2 BATTSW_OPEN
O
Battery open signal output terminal
159
U_XDREQ
I
USB DMAC transfer request signal input terminal
160
S_XDACK
O
MG IC DMAC transfer strobe signal output terminal
161
VCC
—
Power supply terminal
162
PF6 HP_BB1/2
O
Headphone bus boost 1/2 switch signal output terminal
163
S_XDREQ
I
MG IC DMAC transfer request signal input terminal
164
VSS
—
Ground
165
AVSS
—
Analog ground
166
PI7 STOP
I
STOP key signal input terminal
167
PI6
I
Input port terminal
168
PI5
I
Input port terminal
169
PI4 HIDC
I
HIGH DC input detection signal input terminal
170
AN3 AN_DCV
I
DC voltage signal input terminal
171
PI2 BATT
I
Battery signal input terminal
172
AN1 AN_KEY
I
Key signal input terminal
173
PI0 AN_BATTV
I
Battery voltage signal input terminal
174
PH1 JOG
I
JOG PLAY/PAUSE key signal input terminal
175
PH0 HOLD
I
HOLD key signal input terminal
176
AVCC
I
Analog power supply input terminal
04
6
5
46
8
48
47
45
42
42
43
44
3
11
12
9
13
4
14
13
23-34, 37-40
D0-D15
D0-D15
A1-A6
CPU
REGISTER
DEVICE
CONTROL
UNIT
END POINT
BUFFER
(3k BYTE FIFO)
USB
PERIPHERAL
CIRCUIT
CLOCK
CONTROL
(OSCILLATOR/
PLL)
USB
TRANSCEIVER
INSTRUCTION
REGISTER
INSTRUCTION
DECODE
CONTROL
&
CLOCK
GENERATION
ADD
BUFFER
/DECODER
DATA
REGISTER
EEPROM
BATTERY
CHARGER
(1/2)
SERIAL
INTERFACE
ENGINE
65-62,59-54,52,50-44
108-105,102-96,94,92-89
157
159
4
156
15
14
25-18,8-1,48
29-36,38-45
115
113
11
6
2
1
3
4
1
2
XWRL
R/W
XLB
XUB
XWRH
OUT
INVERTER
IC711
15
4
1
2
XWRL
XRD
OUT
INVERTER
IC712
14
26
28
4
1
2
XWRH
XRD
OUT
INVERTER
IC713
69
68
73
70
1
71
TRST
DACK
DREQ
CS
INT
RD
WR
RESET
A1-A6
1
1
2
2
3
4
8
16
18
17
PD31 F SO
XCS2 SRAM XCS
XRD
U XDACK
U XDREQ
XCS3 U XCS
XIRQ7 U XIRQ
XWRLH S XWRH
XWRLL S XWRL
PD28 U XRST
XCS5 F XCS
PD29 F CLK
PD26 F RST
PD30 F SI
5
10
5
D0-D15
A1-A17
A0-A17
16
16
D0-D15
D0-D15
A0-A17
I/O1-I/O16
A0-A16
XCE1 XOE
S-RAM
IC708
MS BS
BS
DIO
INS
SCLK
SCLK
MS DIO
X701
4MHz
EJECT
MECHANISM
BLOCK
PA19 MS INS
MS CLK
MS CLK
XTAL
EXTAL
X704
12MHz
USB VCC
+3.3V
USB D-
USB D+
D-
D+
TR ON
VBUS
XIN
XOUT
XCS
RESET
DI
XSCK
DO
EEPROM
IC705
SYSTEM CONTROL
IC701(1/3)
UNIVERSAL SERIAL BUS DEVICE CONTROL
IC704
4
16
6
17-22
• SIGNAL PATH
: DIGITAL
4-2. BLOCK DIAGRAM — AUDIO SECTION (1/2) —
– 19 –
– 20 –
NW-MS7
(Page
21)
04
5
37
6 163 160 148
88
48 49
65
15
51
52
58
62
61
59
64
25
28
29
31
32
38
33
36
DES
CONTROL
108,107,105,104,
102,101,99,98
93,92,90,89,87,86,82,
80,77,76,74,73,71-68
AUDIO
INTERFACE
CLOCK
GENERATOR
&
RESET
CIRCUIT
DSP CORE
DATA
RAM
&
ROM
PROGRAM
ROM
MICRO
COMPUTER
INTERFACE
ATRAC
DATA
INTERFACE
20 23 24
1
12
9
5
6
4
SERIAL
INPUT
INTERFACE
8-TIMES
OVER •
SAMPLING
DIGITAL
FILTER
(MULTI
FUNCTION)
CLOCK
MANAGER
BCKIN
XTI
LRCIN
DIN
MODE
CONTROL
MULTI-LEVEL
MODULATOR
CR LPF
AMP
18 17 16
15
31 32 28
19
72
80
144 145 147
2 3
97
6 8
9 11
13
1
1
2
2
3
4
5
EXTAL
FS512F
LRCK
XBCK
ACLK
ACDO
XABS
ACDI
XARQ
DODT
LRCK
BCK
BCK
ACLK
ACDI
XABS
ACDI
XABS
ACDO
XARQ
VOUTL
VOUTR
RESET
MT
SW
22
21
BST
SW
BEEP
SWITCH
Q304
BB1/2
SWITCH
Q301
16
17
MTSW
INA
INB
BSTSW
24
8
4
85
2
9
10
11
12
23
15
VREF
BEEP
i
J303
17 18 19
5
6
7
X706
32.768kHz
2
3
1
OSCILLATION
CIRCUIT
FREQUENCY
DIVISION,
TIMING
PRODUCTION
SERIAL
INTERFACE
COMPARATOR
XIN
XINT
XOUT
INT
REGISTER
SIO
XSCK
CS
PC22 S CLKOFF
XCS1 S XCS
S XDREQ
S XDACK
XIRQ0 S XIRQ
PD16 S XRST
PB7 G SCLK
PB6 G SWDT
PB17 G XLAT
PD27 G XRST
PE12 DA ML
PE13 DA MC
PE15 DA MD
PD21 DA XRST
PD19 HP MUTING
PE17 HP BBON
PF6 HP BB1/2
PD18 HP BEEP
PA8 RTC CE
PA4 RTC CLK
PA0 RTC SIO
149
84
162
BEEPOUTA
BEEPOUTB
BEEPIN
REALTIME CLOCK
IC706
D/A CONVERTOR PROCESSOR
IC301
HEADPHONE AMP
IC302
VREF
LPF1
BSTNF1
LPF2
OUTA
OUTB
BSTNF2
45
43
X702
22.5792MHz
XCS
XRD
AB8
AB0-AB7
A0-A7
DB0-DB15
D0-D15
XWRH
XWRL
XDREQ
XDACK
XIRQ
XRST
SCLK
FS256
BCK
XTLO
XTLI
SWDT
XLAT
ATRAC3 ENCODER/DECODER
IC703
MAGIC GATE IC
IC702
ATRAC
INTERFACE
FIFO0
FIFO1
16
8
16
16
ML/MUTE
MC/DM1
MD/DM0
RSTB
PWB
PWA
ADD
BST
CLOCK
GENERATOR
SYSTEM CONTROL
IC701(2/3)
CPU INTERFACE
• SIGNAL PATH
: DIGITAL
: ANALOG
4-3. BLOCK DIAGRAM — AUDIO SECTION (2/2) —
NW-MS7
– 21 –
– 22 –
(Page
20)
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