Sony NW-MS11 Service Manual ▷ View online
34
NW-MS11
Pin No.
Pin Name
I/O
Description
171
VDDIO2
—
Power supply terminal (+2.8V)
172
VSSIO2
—
Ground terminal
173 to 180
FRIO8 to FRIO15
I/O
Not used (open)
181
VDDIO2
—
Power supply terminal (+2.8V)
182
VSSIO2
—
Ground terminal
183 to 187
FRCE0 to FRCE4
O
Not used (pull up)
188
FRWE
O
Not used (pull up)
189
FRRE
O
Not used (pull up)
190
FRCLE
O
Not used (open)
191
FRALE
O
Not used (open)
192
FRWP
O
Not used (pull up)
193
VDDIO2
—
Power supply terminal (+2.8V)
194
FRREADY
I
Not used (fixed at “L”)
195
VSSIO2
—
Ground terminal
196
VSSIO3
—
Ground terminal
197
FS256
O
Clock signal (11.2896 MHz) output to the D/A converter (IC3100)
198
PCMO
O
Digital audio signal output to the D/A converter (IC3100)
199
XCSADA
—
Not used (open)
200
CDTO
O
Not used (open)
201
CCLK
—
Not used (open)
202
DGSDO
O
Not used (open)
203
VDDIO3
—
Power supply terminal (+1.8V)
204
BCK
O
Bit clock signal output to the D/A converter (IC3100)
205
LRCK
O
L/R sampling clock signal output to the D/A converter (IC3100)
206
VSSIO3
—
Ground terminal
207
DGSDI
I
Not used (fixed at “L”)
208
CDTI
I
Not used (fixed at “L”)
209
PCMI
I
Not used (fixed at “L”)
210
VDDIO3
—
Power supply terminal (+1.8V)
211
BUSPLU
I
Not used (fixed at “L”)
212 to 217 TEST0 to TEST5
I
For test terminal Normally open
218
VSSCORE
—
Ground terminal
219, 220
MD6, MD5
I
Mode setting input terminal Fixed at “H” in this set
221
MD4
I
Mode setting input terminal Fixed at “L” in this set
222
MD3
I
Mode setting input terminal Fixed at “H” in this set
223, 224
MD2, MD1
I
Mode setting input terminal Fixed at “L” in this set
225
MD0
I
Mode setting input terminal Fixed at “H” in this set
226
NMI
I
Not used (fixed at “L”)
227
VDDCORE
—
Power supply terminal (+1.8V)
228
TCLK
I
Not used (open)
229
TDI
I
Not used (open)
230
TMS
I
Not used (open)
231
XTRST
I
Not used (open)
232
TCLKD
I
Not used (open)
233
TDID
I
Not used (open)
234
TMSD
I
Not used (open)
35
NW-MS11
Pin No.
Pin Name
I/O
Description
235
XTRSTD
I
Not used (open)
236
VSSCORE
—
Ground terminal
237
TDOD
O
Not used (open)
238
TDO
O
Not used (open)
239
VDDCORE
—
Power supply terminal (+1.8V)
240, 241
MSEL0D, MSEL1D
I/O
Not used (open)
242, 243 MSEL1, MSEL0
I/O
Not used (open)
244
VSSIO1
—
Ground terminal
245
VDDIO1
—
Power supply terminal (+2.8V)
246 to 253
D15 to D8
I/O
Two-way data bus with the flash memory (IC5000), S-RAM (IC5600) and CXD1859GA
(IC8000)
(IC8000)
254
VSSIO1
—
Ground terminal
255
VDDIO1
—
Power supply terminal (+2.8V)
256
D7
I/O
Two-way data bus with the flash memory (IC5000), S-RAM (IC5600) and CXD1859GA
(IC8000)
(IC8000)
36
NW-MS11
•
MAIN BOARD IC8000 CXD1859GA
Pin No.
Pin Name
I/O
Description
1
CLKSEL2
I
Clock mode setting terminal Fixed at “L” in this set
2
XTAL0
O
Sub system clock output terminal (22.5MHz) Not used (open)
3
EXTAL0
I
Sub system clock input terminal (12MHz) Connected to XTAL1 (pin9) in this set
4
VSS0
—
Ground terminal
5
CLKSEL3
I
Clock mode setting terminal Fixed at “H” in this set
6
CLKSEL4
I
Clock mode setting terminal Fixed at “L” in this set
7
VDD0
—
Power supply terminal (+1.8V)
8
VDE0
—
Power supply terminal (+2.8V)
9
XTAL1
O
Main system clock output terminal (12MHz)
10
EXTAL1
I
Main system clock input terminal (12MHz)
11
OSCSTP
O
Stop oscillating signal output terminal “L”: stop oscillating Not used (open)
12
VSS1
—
Ground terminal
13
RST
I
Reset signal input from the system controller (IC7001) or reset signal generator (IC9007)
14
AVS1
—
Ground terminal (for PLL)
15
AVD1
—
Power supply terminal (+2.8V) (for PLL)
16
FS256O
O
Clock signal (11.2896 MHz) output terminal Not used (open)
17
DP0
O
Ready/busy signal output to the EEPROM (IC6002) “L”: busy, “H”: ready
18
DP1
O
Reset signal output to the EEPROM (IC6002)
19
VSS2
—
Ground terminal
20
BS
O
Bus state signal output to a memory stick
21
SCLK
O
Clock signal output to a memory stick
22
DIO
I/O
Two-way data bus with a memory stick
23
VDE1
—
Power supply terminal (+2.8V)
24
VDD1
—
Power supply terminal (+1.8V)
25
DP2
O
USB communication on/off control signal output “H”: USB communication on
26
INS
I
Memory stick in/out detection signal input “L”: memory stick is inserted
27
VSS3
—
Ground terminal
28
UDP
I/O
Two-way data bus of UBS data
29
AVD2
—
Power supply terminal (+2.8V)
30
UDM
I/O
Two-way data bus of UBS data
31
BCLK
I
Bit clock signal input terminal Not used (open)
32
LRCK
I
L/R sampling clock signal input terminal Not used (open)
33
SDO
O
Audio signal output terminal Not used (open)
34
VSS4
—
Ground terminal
35
SDI
I
Audio signal input terminal Not used (fixed at “L”)
36
DAOUT
O
Digital audio signal output terminal Not used (open)
37
DAIN
I
Digital audio signal input terminal Not used (fixed at “L”)
38
VDE2
—
Power supply terminal (+2.8V)
39 to 44
DB0 to DB5
I/O
Two-way data bus with the flash memory (IC5000), S-RAM (IC5600) and system controller
(IC7001)
(IC7001)
45
VDD2
—
Power supply terminal (+1.8V)
46
VSS5
—
Ground terminal
47 to 52
DB6 to DB11
I/O
Two-way data bus with the flash memory (IC5000), S-RAM (IC5600) and system controller
(IC7001)
(IC7001)
53
VDE3
—
Power supply terminal (+2.8V)
(DIGITAL SIGNAL PROCESSOR, MAGIC GATE CORE, MEMORY STICK INTERFACE, USB INTERFACE)
37
NW-MS11
Pin No.
Pin Name
I/O
Description
54 to 56
DB12 to DB14
I/O
Two-way data bus with the flash memory (IC5000), S-RAM (IC5600) and system controller
(IC7001)
(IC7001)
57
VSS6
—
Ground terminal
58
DB15
I/O
Two-way data bus with the flash memory (IC5000), S-RAM (IC5600) and system controller
(IC7001)
(IC7001)
59 to 63
ADR0 to ADR4
I
Address signal input from the system controller (IC7001)
64
VSS7
—
Ground terminal
65, 66
ADR5, ADR6
I
Address signal input from the system controller (IC7001)
67
VDD3
—
Power supply terminal (+1.8V)
68
VDE4
—
Power supply terminal (+2.8V)
69 to 71
ADR7 to ADR9
I
Address signal input from the system controller (IC7001)
72
VSS8
—
Ground terminal
73 to 77
ADR10 to ADR14
I
Address signal input from the system controller (IC7001)
78
RD
I
Read enable signal input from the system controller (IC7001)
79
VSS9
—
Ground terminal
80
WRU
I
Write enable signal input from the system controller (IC7001) (upper byte)
81
WRL
I
Write enable signal input from the system controller (IC7001) (lower byte)
82
CS
I
Chip select signal input from the system controller (IC7001)
83
VDE5
—
Power supply terminal (+2.8V)
84
VDD4
—
Power supply terminal (+1.8V)
85
IRQ
O
Interrupt request signal output to the system controller (IC7001)
86
DREQ0
O
USB DMA request signal output terminal Not used (open)
87
VSS10
—
Ground terminal
88
DACK0
I
USB DMA acknowledge signal input terminal Not used (open)
89
TEST0
O
For test terminal Normally open
90
TEST1
I
For test terminal Normally open
91
SIOSI
I
Serial data input from the EEPROM (IC6002)
92
SIOSO
O
Serial data output to the EEPROM (IC6002)
93
SIOCS
O
Chip select signal output to the EEPROM (IC6002)
94
VSS11
—
Ground terminal
95
SIOCK
O
Serial data transfer clock signal output to the EEPROM (IC6002)
96
ACLK
I
ATRAC3 data transfer clock signal input terminal Not used (fixed at “L”)
97
ARQ
O
ATRAC3 data request signal output terminal Not used (open)
98
VDE6
—
Power supply terminal (+2.8V)
99
ABS
I
ATRAC3 data request signal input terminal Not used (fixed at “L”)
100
ACDO
O
ATRAC3 data output terminal Not used (open)
101
ACDI
I
ATRAC3 data input terminal Not used (fixed at “L”)
102
DP3
O
System wake up request signal output to the system controller (IC7001)
103
TKURST
I
Not used (fixed at “L”)
104
TKDBG
I
Not used (fixed at “L”)
105
VDD5
—
Power supply terminal (+1.8V)
106
VSS12
—
Ground terminal
107
TKTCK
I
Not used (fixed at “L”)
108
TKTDI
I
Not used (fixed at “L”)
109
TKTMS
I
Not used (fixed at “L”)
110
TKTDO
O
Not used (open)
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