Sony MHC-VX333 (serv.man2) Service Manual ▷ View online
46
HCD-VX333
• VIDEO CD BOARD IC502 M30620MCA-B22FP (CD MECHANISM CONTROLLER)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42, 43
44
45
46
47
48
49
50
51
I/O
I
O
O
O
O
O
I
I
—
O
O
I
O
—
I
—
I
I
O
I
O
O
I
O
I
O
O
O
I/O
I/O
O
I
O
O
O
I
O
O
I
O
I
O
I
I
O
O
O
O
O
I
Description
Internal status (SENSE) signal input from the CXD3008Q (IC101)
Sense serial data reading clock signal output to the CXD3008Q (IC101)
Y resolution output
Chroma level output
Serial data transfer clock signal output to the CXD3008Q (IC101)
Not used (open)
Remote control signal input terminal Not used (open)
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
Ground terminal
Muting on/off control signal output to the CXD3008Q (IC101) “H”: muting on
Clock selection signal output to the CXD3008Q (IC101) “L”: 16.9344 MHz (double speed), “H”: 33.8688 MHz
Reset signal input from the system controller (IC501) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
Main system clock output terminal (10 MHz)
Ground terminal
Main system clock input terminal (10 MHz)
Power supply terminal (+5V)
Non-maskable interrupt input terminal (fixed at “H” in this set)
Subcode sync (S0+S1) detection signal input from the CXD3008Q (IC101)
Not used (open)
Interrupt request signal input from the MPEG video/audio decoder (IC505)
HSEL serial signal output to the MPEG video/audio decoder (IC505)
Serial data latch pulse output to the D/A converter (IC509) “L” active
HRDY serial signal input from the MPEG video/audio decoder (IC505)
Reset signal output to the MPEG video/audio decoder (IC505) “L”: reset
Horizontal sync signal input
Burst gate pulse signal output
AGC hold signal output
Laser power selection signal output to the CXA2568M (IC103) “H”: laser on
I
2
C clock signal from CD mechanism control (IC501).
I
2
C data signal from CD mechanism control (IC501).
Serial data output to the MPEG video/audio decoder (IC506) and D/A converter (IC509)
Serial data input from the MPEG video/audio decoder (IC506)
Serial data transfer clock signal output to the MPEG video/audio decoder (IC506) and D/A converter (IC509)
RTS signal to serial port (check connector).
Not used (open)
Sub-code Q data input from the CXD3008Q (IC101)
Sub-code Q data reading clock signal output to the CXD3008Q (IC101)
Power on/off control signal output terminal Not used (open)
Ready signal input terminal Not used (fixed at “H”)
Not used (open)
Hold signal input terminal Not used (fixed at “H”)
Not used (open)
OSD language select input terminal “H”: English, “L”: China
Vertical sync signal input
Bus write signal output.
Not used (open)
Audio muting on/off control signal output terminal “L”: muting on Not used (open)
Loading motor drive signal output terminal Not used (open)
Loading motor drive signal output terminal Not used (open)
Disc detection (load in) switch input terminal Not used (fixed at “H”)
Pin Name
SENSE
SENSE CLK
RESOLUTION
CROMA LEVEL
DSP CLK
TSENS
REMOTE IN
BYTE
CN VSS
DSP MUTE
CTRL1
XRESET
XOUT
VSS
XIN
VCC
NMI
SCOR
DSENS
CL680 HINT
CL680 HSEL
DF LATCH
CL680 HRDY
680 RESET
H.SYNC IN
BGP
LPH
LD ON
I2C.CLK
I2C.DATA
DATA1O
DATA1I
CLK1
RTS1
XVLEVEL.DOWN
SUBQ DATA
SUBQ CLK
P.ON
BUS XRDY
BUS
BUS XHOLD
BUS
OSD.LANGUAGE
VSYNC
BUS XWRL
LO.BOOST
AUDIO MUTE
LOAD OUT
LOAD IN
INSW
47
HCD-VX333
Pin No.
52
53
54
55
56
57 to 59
60, 61
62
63
64
65
66 to 72
73
74
75
76
77
78
79
80
81 to 88
89
90 to 92
93
94
95
96
97
98
99
100
I/O
I
I
I
—
—
—
—
—
—
—
O
O
O
I
I
I
O
O
O
O
I/O
—
I
I
—
O
—
O
I
—
—
Description
Disc detection (load out) switch input terminal Not used (fixed at “H”)
Destination setting terminal (fixed at “L”)
Destination setting terminal (fixed at “L”)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Power supply terminal (+5V)
Not used (open)
Ground terminal
Video muting on/off control signal output
Address signal output for the external device
LED drive signal output for the self diagnosis indicator (D502) Normally: “L” (LED on)
Setting terminal for the test mode 1 (for VCD check) Normally: fixed at “H” (“L”: test mode)
Setting terminal for the test mode 2 (for SERVO check) Normally: fixed at “H” (“L”: test mode)
Setting terminal for the test mode 3 Normally: fixed at “H” (“L”: test mode) Not used (fixed at “H”)
System reset signal output to the CXD3008Q (IC101), BA5974FP (IC102) and D/A converter (IC509) “L”: reset
Standby on/off control signal output terminal Not used (open)
Chip select signal output terminal Not used (open)
Blank control signal output terminal Not used (open)
Two-way data bus with the external device Not used (open)
Not used.
Key input terminal Not used (fixed at “H”)
Video system select input terminal (open: AUTO)
Not used.
Serial data output to the CXD3008Q (IC101)
Ground terminal (for A/D conversion)
Serial data latch pulse output to the CXD3008Q (IC101)
Reference voltage (+5V) input terminal (for A/D conversion)
Power supply terminal (+5V) (for A/D conversion)
Not used.
Pin Name
OUTSW
MODEL1
MODEL2
TBLL
TBLR
ENC1 to ENC3
VCC
VSS
V.MUTE
A6 to A0
TEST LED
TEST1
TEST2
TEST3
DEVICE RESET
STANDBY
FL CS
FLBLK
D7 to D0
MIC CTRL
KEY1 to KEY3
NT/PAL
MUSIC VOL
DSP DATA
AVSS
DSP LATCH
VREF
AVCC
AMP ON
48
HCD-VX333
6-24. IC BLOCK DIAGRAMS
IC101 BA1450 (MAIN BOARD)
IC102 LC72130 (MAIN BOARD)
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
AM
OSC
AM
MIX
AM IF
FM
IF
FM
DET
AM
DET
SD
DET
AGC
LED
DRIVER
COMP
SD
SW
VCO
PD
1/2
DECODER
VREG
1/2
FM IN
FM DET
TUNED
STEREO
IF OUT
R OUT
L OUT
AM/FM
FM/AM DET OUT
AM MPX IN
FM MPX IN
IN REQ MUTE
FM SD ADJ
VCC
GND
AM OSC OUT
AM OSC
VCO STOP
AM RF IN
AM IF IN
AM AGC
AM MIX OUT
FM BAND WIDTH
V . REG
1
2
3
4
5
6
7
8
XIN
B03
CE
IFIN
AOUT
2
AIN1
AIN2
D1
CL
B04
D0
B01
I01
B02
XOUT
PD1
VSS
PD2
FMIN
AMIN
AOUT1
VDD
I02
B05
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PHASE DETECTOR
CHARGE PUMP
SWALLOW COUNTER
1/16.1/17 4bits
SWALLOW COUNTER
1/16.1/17 4bits
POWER
ON
RESET
1/2
C B
I / F
I / F
REFERENCE
DIVIDER
REFERENCE
DIVIDER
C B
I / F
I / F
2
DATA SHIFT REGISTER
LATCH
49
HCD-VX333
IC201 TA8189N (MAIN BOARD)
IC701 BA6956AN (DRIVER BOARD)
IC101 CXD3008Q (BD BOARD)
CH2/A CH2/B
NF
VCC
CG
NF
ALC
METAL
OUT
PRE
OUT
OUT
TAPE A
/TAPE B
REC
OUT
OUT
REC
IN
CH1/A CH1/B
NF
GND1
M/H
NF
CH2
CH2
ALC
M/N
CH1
GND
GND
CH1
+
–
+
–
+
–
+
–
A/B
GND
METAL
OUT
PRE
OUT
OUT
MIX
OUT
REC
OUT
OUT
REC
IN
IREF
VREF2
VREF1
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
26 27
28
29 30 31 32 33 34
35 36 37
38 39 40
TES1
SE
FE
VC
TFDR
DVSS1
FRDR
FFDR
TRDR
SRDR
SFDR
DVDD1
FST0
SSTP
TES1
80 79 78 77 76
75 74 73
72 71 70 69 68 67 66
XTSL
PCMD
BCK
EMPH
XOLT
XTA1
XTA0
SOUT
SOCK
SQSO
SQCK
SCSY
EXCK
EXCK
DVSS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
XRST
VDD
MDP
LOCK
PWM1
DFCT
MIRR
COUT
DVSS
WDCK
FDK
SCOR
C2P0
XPCK
XUGF
WFCK
ATSK
SENS
CLOK
XLAT
DATA
SENS
CLOK
XLAT
DATA
MUTE
SCLK
GFS
C4M
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
65
64
47
46
45
44
43
42
41
LRCK
DOUT
VPC0
ASYE
MD2
FIL0
CLTV
ASY0
ASY1
RFAC
AVSS1
FIL1
PCO
DVDD2
BIAS
V16M
CE
TE
RFDC
AD10
AVSS0
1GEN
AVDD
CLOCK
GENERATOR
ASYMMETY
CORRECTOR
DIGITAL
PLL
EFM
DEMODURATOR
DIGITAL
PLL
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
SERVO
INTERFACE
SUB
CODE
PROCESSOR
DIGITAL
OUT
ERROR
CORRECTOR
32K
RAM
D/A
INTERFACE
MIRR
DFCT
FOK
OP
AMP
ANALOG
SW
A/D
CONVERTER
FOCUS SERVO
TRACKING
SERVO
SERVO DSP
SLED PWM
GENERATOR
TRACKING PWM
GENERATOR
FOCUS PWM
GENERATOR
PWM GENERATOR
SLED SERVO
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